Interview MCQ Set 1
1. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
Answer
Answer: d [Reason:] The SFR addresses of the ports P0, P1, P2 and P3 are 80H, 90H, A0H and B0H respectively.
2. Each port line of a port can individually source a current of upto
a) 0.2 mA
b) 0.25 mA
c) 0.5 mA
d) 0.75 mA
Answer
Answer: c [Reason:] Each port line of a port can individually source a current of upto 0.5 mA.
3. Each port line of a port can individually sink a current of upto
a) 2 mA
b) 8 mA
c) 5 mA
d) 1 mA
Answer
Answer: b [Reason:] Each port line of a port can individually sink a current of upto 8 mA.
4. The number of TTL inputs that can be sinked by the port 0 when a logic 0 is sent to a port line as an output port is
a) 2
b) 4
c) 6
d) 8
Answer
Answer: d [Reason:] When a logic 0 is sent to a port line as an output port, it can sink 8 LS TTL inputs. Port 0 is used as data bus during external interfacing whenever required.
5. The open drain bidirectional (input or output) port with internal pullups is
a) Port 0
b) Port 1
c) Port 2
d) Port 3
Answer
Answer: a [Reason:] Port 0 is an open drain bidirectional (input or output) port with internal pullups. Port 1, Port 2, Port 3 are 8-bit bidirectional ports.
6. The port that can source or sink 4 LS TTL inputs when being used as an output port on each of its line is
a) Port 1
b) Port 2
c) Port 3
d) all of the mentioned
Answer
Answer: d [Reason:] The ports P1, P2 and P3 can source or sink 4 LS TTL inputs when being used as an output port on each of its line.
7. The port that will source a current of 500 micro amperes when being used as input ports is
a) 0.5 mA
b) 0.25 mA
c) 250 micro amperes
d) 500 micro amperes
Answer
Answer: d [Reason:] Port 3 pins which are externally pulled low when being used as input pins will source current of 500 micro amperes.
8. If the EA(active low) signal is grounded then the execution
a) directly start from main memory
b) directly start from 16 bit address in main memory
c) directly start from 16 bit address in program memory
d) directly start from RAM
Answer
Answer: c [Reason:] For interfacing external program memory, EA(active low) pin must be grounded. If the EA(active low) signal is grounded then the execution will start directly from the 16-bit address 0000H in external program memory.
9. When the port lines of a port are to be used as input lines then the value that must be written to the port address is
a) F0H
b) 0FH
c) FFH
d) 00H
Answer
Answer: c [Reason:] When the port lines of a port are to be used as input lines then ‘FF’H must be written to the port address.
10. Port 1 lines are used during programming of
a) external EPROM and EEPROM
b) external ROM and RAM
c) internal ROM and RAM
d) internal EPROM and EEPROM
Answer
Answer: d [Reason:] Port 1 lines are used as lower byte of 16-bit address bus during programming of internal EPROM or EEPROM.
11. The configuration in which each LED receives operating current of 8 mA from power supply while the port lines sink the current on each port line is
a) common port configuration
b) common anode configuration
c) common cathode configuration
d) none of the mentioned
Answer
Answer: b [Reason:] The common anode configuration is preferred to that of other configurations as in common anode configuration, each LED receives operating current of 8 mA from power supply while the port lines sink the current on each port line.
Interview MCQ Set 2
1. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Answer
Answer: b [Reason:] Since joystick is an input device, it reads data from the external devices.
2. The example of output device is
a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
Answer
Answer: d [Reason:] The output device transfers data from microprocessor to the external devices.
3. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Answer
Answer: c [Reason:] The input activity is similar to read operation and the output activity is similar to write operation.
4. The operation, IOWR (active low) performs
a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Answer
Answer: b [Reason:] IOWR (active low) operation means writing data to an output device and not an input device.
5. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Answer
Answer: c [Reason:] If the output port is to source large currents, the port lines must be buffered. So, the latch is used as it acts as good output port.
6. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Answer
Answer: c [Reason:] More current should not be sourced or sinked from data lines while reading to avoid loading.
7. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Answer
Answer: d [Reason:] A tristate buffer is used as an input device to overcome loading.
8. The chip 74LS245 is
a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
Answer
Answer: d [Reason:] The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used as an 8-bit input port. But while using as an input device, only one direction is useful.
9. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Answer
Answer: a [Reason:] If DIR is 1, then the direction is from A(inputs) to B(outputs).
10. In memory-mapped scheme, the devices are viewed as
a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Answer
Answer: b [Reason:] In memory-mapped scheme, the devices are viewed as memory locations and are addressed likewise.
Interview MCQ Set 3
1. The CPU of 80286 contains
a) 16-bit general purpose registers
b) 16-bit segment registers
c) status and control register
d) all of the mentioned
Answer
Answer: d [Reason:] The CPU of 80286 contains same set of registers as in 8086.
2. The bits that are modified according to the result of the execution of logical and arithmetic instructions are called
a) byte addressable bit
b) control flag bits
c) status flag bit
d) none of the mentioned
Answer
Answer: c [Reason:] The flag register bits, D0, D2, D4, D6, D7 and D11 are modified according to the result of the execution of logical and arithmetic instructions. These are called as status flag bits.
3. The flags that are used for controlling machine operation are called
a) status flags
b) control flags
c) machine controlled flags
d) all of the mentioned
Answer
Answer: b [Reason:] The flags such as trap flag (TF) and Interrupt flag (IF) bits are used for controlling the machine operation, and thus they are called control flags.
4. The additional field that is available in 80286 is
a) I/O Privilege field
b) nested task flag
c) protection enable
d) all of the mentioned
Answer
Answer: d [Reason:] The additional fields available in 80286 flag register are, I/O Privilege field, nested task flag, protection enable, and monitor processor extension.
5. Which of the block is not considered as a block of architecture of 80286?
a) address unit
b) bus unit
c) instruction unit
d) control unit
Answer
Answer: d [Reason:] The CPU may be viewed to contain four functional parts and they are
i) Address Unit
ii) Bus Unit
iii) Instruction Unit
iv) Execution Unit.
6. The unit that is responsible for calculating the address of instructions, and data that the CPU wants to access is
a) bus unit
b) address unit
c) instruction unit
d) control unit
Answer
Answer: b [Reason:] The address unit is responsible for calculating the address of instructions, and data that the CPU wants to access. Also the address lines derived by this unit may be used to address different peripherals.
7. The process of fetching the instructions in advance, and storing in the queue is called
a) mapping
b) swapping
c) instruction pipelining
d) storing
Answer
Answer: c [Reason:] The instructions are fetched in advance and stored in a queue to enable faster execution of the instructions. This concept is known as instruction pipelining.
8. The CPU must flush out the prefetched instructions immediately following the branch instruction in
a) conditional branch
b) unconditional branch
c) conditional and unconditional branches
d) none of the mentioned
Answer
Answer: b [Reason:] In case of unconditional branch, the CPU will have to flush out the prefetched instructions, immediately following the branch instruction.
9. The device that interface and control the internal data bus with the system bus is
a) data interface
b) controller interface
c) data and control interface
d) data transreceiver
Answer
Answer: d [Reason:] The data transreceivers interface and control the internal data bus with the system bus.
10. The register bank of Execution Unit of 80286 is used as
a) for storing data
b) scratch pad
c) special purpose registers
d) all of the mentioned
Answer
Answer: d [Reason:] The execution unit contains the register bank, used for storing the data as scratch pad, or used as special purpose registers.
11. Which of the following is not an interrupt generated by 80286?
a) software interrupts
b) hardware or external interrupts
c) INT instruction
d) none of the mentioned
Answer
Answer: d [Reason:] The interrupts generated by 80286 may be divided into 3 categories as external or hardware interrupts, INT instruction or software interrupts and interrupts generated by exceptions.
12. For which of the following instruction does the return address point to instruction causing exception?
a) divide error exception
b) bound range exceeded exception
c) invalid opcode exception
d) all of the mentioned
Answer
Answer: d [Reason:] For the instructions, divide error, bound range exceeded and invalid opcode exceptions, the return address points to the instruction causing exception.
13. The instruction that comes into action, if the trap flag is set is
a) maskable interrupt
b) non-maskable interrupt
c) single step interrupt
d) breakpoint interrupt
Answer
Answer: c [Reason:] Single step interrupt is an internal interrupt that comes into action, if the trap flag (TF) is set.
14. The interrupt that has the highest priority among the following is
a) Single step
b) NMI (non-maskable interrupt)
c) INTR
d) Instruction exception
Answer
Answer: d [Reason:] The instruction exception has the highest priority followed by single step, NMI and INTR instrution.
15. The interrupt that has the lowest priority among the following is
a) Processor extension segment overrun
b) INTR
c) INT instruction
d) NMI
Answer
Answer: c [Reason:] The INT instruction has the lowest priority. The order of priority of interrupts from high to low is
1) instruction exception
2) single step
3) NMI
4) processor extenstion segment overrun
5) INTR
6) INT instruction.
Interview MCQ Set 4
1. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
Answer
Answer: b [Reason:] If an external device or a signal interrupts the processor from outside then it is an external interrupt.
2. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
Answer
Answer: a [Reason:] The internal interrupt is generated internally by the processor circuit or by the execution of an interrupt instruction.
3. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
Answer
Answer: b [Reason:] Since the keyboard is external to the processor, it is an external interrupt.
4. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
Answer
Answer: d [Reason:] Since the interrupts occur within the processor itself, they are called internal interrupts.
5. The interrupt request that is independent of IF flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
Answer
Answer: d [Reason:] These requests are independent of IF flag.
6. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
Answer
Answer: c [Reason:] After an interrupt is acknowledged, the CPU computes the vector address from the type of the interrupt that may be passed to the internal structure of the CPU from an interrupt controller in case of external interrupts.
7. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
Answer
Answer: d [Reason:] The contents of IP, CS and PSW are pushed into the stack during the execution.
8. After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
Answer
Answer: b [Reason:] If the trap flag is set then the processor enters the single step execution mode. After the execution, the trap flag is cleared.
9. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
Answer
Answer: c [Reason:] After the execution of the ISR, the control must go to the previous program (may be main program) which was being executed. To execute it, IRET is placed at the end of ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
Answer
Answer: a [Reason:] When the instruction IRET is executed, the contents of flags, IP and CS which were saved at the stack by the CALL instruction are retrieved to the respective registers.
Interview MCQ Set 5
1. Which of the following is an external interrupt?
a) INT0(active low)
b) INT2(active low)
c) Timer0 interrupt
d) Timer1 interrupt
Answer
Answer: a [Reason:] INT0(active low) and INT1(active low) are two external interrupt inputs provided by 8051.
2. The interrupts, INT0(active low) and INT1(active low) are processed internally by flags
a) IE0 and IE1
b) IE0 and IF1
c) IF0 and IE1
d) IF0 and IF1
Answer
Answer: a [Reason:] The interrupts, INT0(active low) and INT1(active low) are processed internally by the flags IE0 and IE1.
3. The flags IE0 and IE1, are automatically cleared after the control is transferred to respective vector, if the interrupt is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer
Answer: b [Reason:] If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are automatically cleared after the control is transferred to respective vector.
4. If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port
Answer
Answer: a [Reason:] If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are controlled by external interrupt sources themselves.
5. The pulses at T0 or T1 pin are counted in
a) timer mode
b) counter mode
c) idle mode
d) power down mode
Answer
Answer: b [Reason:] In counter mode, the pulses are counted at T0 or T1 pin.
6. In timer mode, the oscillator clock is divided by a prescalar
a) (1/8)
b) (1/4)
c) (1/16)
d) (1/32)
Answer
Answer: d [Reason:] In timer mode, the oscillator clock is divided by a prescalar (1/32) and then given to the timer.
7. The serial port interrupt is generated if
a) RI is set
b) RI and TI are set
c) Either RI or TI is set
d) RI and TI are reset
Answer
Answer: c [Reason:] The serial port interrupt is generated if atleast one of the two bits, RI and TI is set.
8. In serial port interrupt, after the control is transferred to the interrupt service routine, the flag that is cleared is
a) RI
b) TI
c) RI and TI
d) None
Answer
Answer: d [Reason:] In serial port interrupt, after the control is transferred to the interrupt service routine, neither of the flags is cleared.
9. The atleast number of machine cycles for which the external interrupts that are programmed level-sensitive should remain high is
a) 1
b) 2
c) 3
d) 0
Answer
Answer: b [Reason:] The external interrupts, programmed level-sensitive should remain high for atleast 2 machine cycles.
10. If the external interrupts are programmed edge sensitive, then they should remain high for atleast
a) 0 machine cycle
b) 2 machine cycles
c) 1 machine cycle
d) 3 machine cycles
Answer
Answer: c [Reason:] If the external interrupts are programmed edge sensitive, then they should remain high for atleast one machine cycle and low for atleast one machine cycle, for being sensed.
