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Interview MCQ Set 1

1. The disadvantage of CISC design processors is
a) low burden on compiler developers
b) wide availability of existing software
c) complex in nature
d) none

View Answer

Answer: c [Reason:] Some computers are used in preference to CISC design due to its low burden on compiler developers and wide availability of existing software. But they are complex in nature.

2. The RISC architecture is preferred to CISC because RISC architecture has
a) simplicity
b) efficiency
c) high speed
d) all of the mentioned

View Answer

Answer: d [Reason:] The RISC architecture is preferred to CISC because RISC architecture is simple, highly efficient and the processors using RISC architecture have high speed.

3. The feature of RISC that is not present in CISC is
a) branch prediction
b) pipelining
c) branch prediction and pipelining
d) none

View Answer

Answer: c [Reason:] A RISC core allows performance enhancing features, such as branch prediction and pipelining. Traditionally, these have only been possible in RISC designs.

4. The feature of hybrid CISC-RISC architecture is
a) consume a lot of power
b) not applicable for mobile applications
c) processed by RISC core
d) all of the mentioned

View Answer

Answer: d [Reason:] The CISC-RISC hybrids continue to consume a lot of power and are not best candidates for mobile and embedded applications.

5. Which of the following is an application of RISC architecture by adding more instructions?
a) multimedia applications
b) telecommunication encoding
c) image conversion
d) all of the mentioned

View Answer

Answer: d [Reason:] By adding more instructions to the RISC architecture, some applications can be run much faster like multimedia applications, telecommunication encoding/decoding, image conversion and video processing.

6. Which of the following processor belongs to hybrid RISC-CISC architecture?
a) Intel Pentium III
b) Intel Itanium 64
c) AMD’s X86-64
d) All of the mentioned

View Answer

Answer: d [Reason:] The processors, Intel Pentium III, Intel Itanium 64 and AMD’s X86-64 consists of hybrid RISC-CISC architecture.

7. In order to implement complex instructions, CISC architectures use
a) macroprogramming
b) hardwire
c) microprogramming
d) none

View Answer

Answer: c [Reason:] In order to implement complex instructions, CISC architectures use microprogramming.

8. The advantage of RISC processors is
a) can operate at high clock frequency
b) shorter design cycle
c) simple and fast
d) all of the mentioned

View Answer

Answer: d [Reason:] The advantages of RISC processors are that they can work at high clock frequency, can be designed, developed and tested more quickly with a high speed.

9. The additional functionality that can be placed on the same chip of RISC is
a) Memory management units
b) Floating point units
c) Memory management and floating point arithmetic units
d) RAM, ROM

View Answer

Answer: c [Reason:] Several extra functionalities, such as memory management units or floating point arithmetic units, can also be placed on the same chip of RISC.

10. The number of clockcycles that take to wait until the length of instruction is known in order to start decoding is
a) 0
b) 1
c) 2
d) 3

View Answer

Answer: a [Reason:] The loading and decoding the instructions in a RISC processor is simple and fast. It is not needed to wait until the length of the instruction is known in order to start the decoding.

Interview MCQ Set 2

1. Which of the following is a resource sharing strategy that had been investigated by the developers?
a) partitioned resources
b) threshold sharing
c) full sharing
d) all of the mentioned

View Answer

Answer: d [Reason:] Several resource sharing strategies have been investigated by the developers. Some of these are 1. Partitioned resources 2. Threshold sharing 3. Full sharing.

2. The feature of hyperthreading is
a) simultaneous multithreading
b) switching is not required
c) effective use of processor resources
d) all of the mentioned

View Answer

Answer: d [Reason:] Hyperthreading used the concept of simultaneous multithreading, where multiple threads can be executed on a single processor without switching.

3. Each logical processor maintains a set of architecture state which consists of
a) general purpose registers
b) machine state register
c) advanced programmed interrupt controller
d) all of the mentioned

View Answer

Answer: d [Reason:] Each logical processor maintains a set of architecture state which consists of 1. Registers including the general purpose registers 2. The control register 3. Advanced programmed interrupt controller 4. Machine state register.

4. A logical processor may be temporarily stalled for
a) including servicing cache misses
b) handling branch mispredictions
c) waiting for results of previous instructions
d) all of the mentioned

View Answer

Answer: d [Reason:] A logical processor may be temporarily stalled for a variety of reasons like including servicing cache misses, handling branch mispredictions and waiting for results of previous instructions.

5. The hyperthreading technology automatically involves the
a) decrease of die area
b) increase of die area
c) decrease of die area to half
d) none

View Answer

Answer: b [Reason:] The hyperthreading technology automatically involves the increase of die area.

6. The instruction that is used when either of the logical processors is idle is
a) HOLD
b) HLDA
c) HALT
d) NONE

View Answer

Answer: c [Reason:] An optimization may require the use of HALT instruction, when either of the two logical processors is idle.

7. The mode that is available when there is only one software thread to execute is
a) single task mode
b) multi task mode
c) single task and multi task mode
d) dual task mode

View Answer

Answer: c [Reason:] When there is only one software thread to execute, there are two modes namely single task mode and multi task mode.

8. The HALT instruction is a privileged instruction that can be only used by
a) execution unit
b) operating system
c) control unit
d) memory unit

View Answer

Answer: b [Reason:] The HALT instruction is a privileged instruction that can be only used by operating system.

9. When the operating system uses HALT instruction on a processor which supports multithreading, the operation moves from
a) Single task to multi task mode
b) ST1 to ST0
c) Multi task to single task mode
d) None

View Answer

Answer: c [Reason:] When the operating system uses HALT instruction on a processor which supports multithreading, the operation moves from multi tasking mode to single tasking mode.

10. The Xeon TM processor on which hyperthreading technology was first implemented consists of
a) one logical processor per physical processor
b) two logical processor per physical processor
c) three logical processor per physical processor
d) zero logical processor per physical processor

View Answer

Answer: b [Reason:] The Xeon TM processor on which hyperthreading technology was first implemented consists of two logical processor per physical processor.

Interview MCQ Set 3

1. The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction

View Answer

Answer: a [Reason:] These instructions are used to copy and transfer the instructions.

2. Which of the following is not a data copy/transfer instruction?
a) MOV
b) PUSH
c) DAS
d) POP

View Answer

Answer: c [Reason:] DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

3. The instructions that involve various string manipulation operations are
a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions

View Answer

Answer: d [Reason:] The string instructions perform operations on strings such as load, move, scan, compare etc.

4. Which of the following instruction is not valid?
a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX

View Answer

Answer: b [Reason:] Both the source and destination operands cannot be memory locations except for string instructions.

5. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2

View Answer

Answer: d [Reason:] The actual current stack-top is always occupied by the previously pushed data. So, the push operation decrements SP by 2 and then stores the two bytes contents of the operand onto the stack.

6. The instruction that pushes the contents of the specified register/memory location on to the stack is
a) PUSHF
b) POPF
c) PUSH
d) POP

View Answer

Answer: c [Reason:] Since PUSH operation transfers data to stack from register or memory location.

7. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2

View Answer

Answer: c [Reason:] The actual current stack top is poped into the specific operand as the contents of stack top memory is stored in AL&SP and further contents of memory location pointed to by SP are copied to AH & SP.

8. The instructions that are used for reading an input port and writing an output port respectively are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT

View Answer

Answer: d [Reason:] The address of the input/output port may be specified directly or indirectly. Example for input port: IN AX, DX ;This instruction reads data from a 16-bit port whose address is in DX and stores it in AX Example for output port: OUT 03H, AL ;This sends data available in AL to a port whose address is 03H.

9. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ

View Answer

Answer: b [Reason:] The translate(XLAT) instruction is used to find codes.

10. The instruction that loads effective address formed by destination operand into the specified source register is
a) LEA
b) LDS
c) LES
d) LAHF

View Answer

Answer: a [Reason:] The instruction,LEA loads effective address and is more useful for assembly language rather than for machine language.

11. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF

View Answer

Answer: c [Reason:] The instruction LAHF(Load AH from lower byte of Flag) may be used to observe the status of all the condition code flags(except overflow flag) at a time.

12. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF

View Answer

Answer: c [Reason:] The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.

13. The instruction that loads the flag register completely from the word contents of the memory location is
a) PUSH
b) POP
c) PUSHF
d) POPF

View Answer

Answer: d [Reason:] POPF is pop flags to stack.

14. The instruction that adds immediate data/contents of memory location specified in an instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV

View Answer

Answer: b [Reason:] ADD instruction adds the data.

15. The instruction that supports addition when carry exists is
a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned

View Answer

Answer: b [Reason:] ADC(Add with Carry) instruction performs the same operation as ADD operation, but adds the carry flag bit to the result.

Interview MCQ Set 4

1. In which of these modes, the immediate operand is included in the instruction itself?
a) register operand mode
b) immediate operand mode
c) register and immediate operand mode
d) none of the mentioned

View Answer

Answer: b [Reason:] In immediate operand mode, the immediate operand is included in the instruction itself.

2. In register address mode, the operand is stored in
a) 8-bit general purpose register
b) 16-bit general purpose register
c) si or di
d) all of the mentioned

View Answer

Answer: d [Reason:] In register address mode, the operand is stored either in one of the 8-bit or 16-bit general purpose registers, or in SI, DI, BX or BP.

3. In which of the following addressing mode, the offset is obtained by adding displacement and contents of one of the base registers?
a) direct mode
b) register mode
c) based mode
d) indexed mode

View Answer

Answer: c [Reason:] In based mode, the offset is obtained by adding displacement and contents of one of the base registers, either BX or BP.

4. In which of the following addressing mode, the offset is obtained by adding displacement, with the contents of SI?
a) direct mode
b) register mode
c) based mode
d) indexed mode

View Answer

Answer: d [Reason:] In indexed mode, the offset is obtained by adding displacement, with contents of an index register, either SI or DI.

5. The address of location of operand is calculated by adding the contents of any of the base registers, with the contents of any of index registers in
a) based indexed mode with displacement
b) based indexed mode
c) based mode
d) indexed mode

View Answer

Answer: b [Reason:] In based indexed mode, the operand is stored at a location, whose address is calculated by adding the contents of any of the base registers, with the contents of any of the index registers.

6. Which of the following is not a data type of 80286?
a) Ordinal or unsigned
b) ASCII
c) Packed BCD
d) None of the mentioned

View Answer

Answer: d [Reason:] The 80286 supports seven data types. They are 1. integer 2. Ordinal (unsigned) 3. pointer 4. string 5. ASCII 6. BCD 7. Packed BCD.

7. The representation of 8-bit or 16-bit signed binary operands using 2’s complement is a data type of
a) Ordinal
b) ASCII
c) Packed BCD
d) integer

View Answer

Answer: d [Reason:] In integer data type, 8-bit or 16-bit signed binary operands are represented using 2’s complement.

8. The instruction that pushes the general purpose registers, pointer and index registers on to the stack is
a) POPF
b) PUSH Imd
c) PUSH*A
d) PUSHF

View Answer

Answer: c [Reason:] The PUSH*A instruction, pushes the general purpose registers, AX, CX, DX and BX, pointer and index registers, SP, BP, SI, DI, on to the stack.

9. While executing the PUSH*A instruction, the stack pointer is decremented by
a) 1 bit
b) 2 bits
c) 4 bits
d) 16 bits

View Answer

Answer: b [Reason:] The stack pointer is decremented by 16 (eight 2-byte registers).

10. The statement that is true for the instruction POP*A is
a) flags are uneffected
b) no operands are required
c) exceptions generated are same as that of PUSH*A
d) all of the mentioned

View Answer

Answer: d [Reason:] The POP*A instruction, pops all the contents of the registers DI, SI, BP, SP, BX, DX, CX and AX from the stack in this sequence, that is exactly opposite to that of pushing.

11. The instruction that multiplies the content of AL with a signed immediate operand is
a) MUL
b) SMUL
c) IMUL
d) None of the mentioned

View Answer

Answer: c [Reason:] The IMUL instruction multiplies the content of AL with a signed immediate operand, and the signed 16-bit result is stored in AX.

12. The instruction that represents the ‘rotate source, count’ is
a) RCL
b) RCR
c) ROR
d) All of the mentioned

View Answer

Answer: d [Reason:] The rotate source, count is a group of four instructions containing RCL, RCR, ROL, ROR.

Interview MCQ Set 5

1. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned

View Answer

Answer: d [Reason:] The memory serves the microprocessor in the same way, whether it is a single microprocessor or a multimicroprocessor.

2. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned

View Answer

Answer: a [Reason:] In a shared bus architecture, only one processor performs bus cycle to fetch instructions or data from the memory.

3. In multiport memory configuration, the processor(s) that address the multiport memory is(are)
a) 1
b) 2
c) 3
d) many

View Answer

Answer: b [Reason:] The processors P1 and P2 address a multiport memory, which can be accessed at a time by both the processors.

4. The memory space of a processor that is mapped to other processor/processors and vice-versa is known as
a) multimicroprocessor system
b) memory technique
c) bus window technique
d) mapping technique

View Answer

Answer: c [Reason:] The bus window technique is the correct method of interconnection between the processors.

5. The disadvantage of bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned

View Answer

Answer: d [Reason:] The disadvantage of bus window technique is that both processors must know implicitly about the existence of bus window, its size and the address map. It also results in loss of effective local memory space.

6. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus

View Answer

Answer: b [Reason:] In crossbar switching type of interconnection topology, several parallel data paths are possible. Each node of the crossbar represents a bus switch.

7. Which of the following is not a type of configuration that is based on physical interconnections between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection

View Answer

Answer: d [Reason:] Based on the physical interconnections between the processors, the configurations are i) star configuration ii) loop or ring configuration iii) complete interconnection iv) regular topologies v) irregular topologies.

8. The configuration, in which all the processing elements are connected to a central switching element, that may be independent processor via dedicated paths is
a) star
b) loop
c) complete
d) irregular

View Answer

Answer: a [Reason:] The switching element controls the interconnections between the processing elements.

9. The configuration that is not suitable for large number of processors is
a) star
b) loop
c) complete
d) regular

View Answer

Answer: c [Reason:] For a large number of processors, the complete interconnection is impractical due to the large number of interconnection paths.

10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular

View Answer

Answer: d [Reason:] In array processor architecture, the processing elements are arranged in a regular fashion.