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Interview MCQ Set 1

1. Which of the following is not an instruction of 8051 instructions?
a) arithmetic instructions
b) boolean instructions
c) logical instructions
d) none

View Answer

Answer: d [Reason:] The 8051 instructions are categorised as 1. Data transfer instructions 2. Arithmetic instructions 3. Logical instructions 4. Boolean instructions 5. Control transfer instructions.

2. The operations performed by data transfer instructions are on
a) bit data
b) byte data
c) 16-bit data
d) all of the mentioned

View Answer

Answer: d [Reason:] The data transfer instructions implement a bit, byte, 16-bit data transfer operations between the SRC(source) and DST(destination) operands.

3. Which of the following is true while executing data transfer instructions?
a) program counter is not accessible
b) restricted bit-transfer operations are allowed
c) both operands can be direct/indirect register operands
d) all of the mentioned

View Answer

Answer: c [Reason:] In data transfer instructions, 1. Program counter is not accessible. 2. Restricted bit-transfer operations are allowed. 3. Both operands can be direct/indirect register operands. 4. BOth operands can be internal direct data memory operands.

4. The logical instruction that affect the carry flag during its execution is
a) XRL A;
b) ANL A;
c) ORL A;
d) RLC A;

View Answer

Answer: d [Reason:] The logical instructions that does not affect the carry flag are, ANL, ORL and XRL. The logical instructions that affect the carry flag during its execution are RL, RLC, RRC and RR.

5. The instruction that is used to complement or invert the bit of a bit addressable SFR is
a) CLR C
b) CPL C
c) CPL Bit
d) ANL Bit

View Answer

Answer: c [Reason:] The instruction, CPL Bit is used to complement or invert the bit of a bit addressable SFR or RAM.

6. The instructions that change the sequence of execution are
a) conditional instructions
b) logical instructions
c) control transfer instructions
d) data transfer instructions

View Answer

Answer: c [Reason:] The control transfer instructions transfer the control of execution or change the sequence of execution conditionally or unconditionally.

7. The control transfer instructions are divided into
a) explicit and implicit control transfer instructions
b) conditional and unconditional control transfer instructions
c) auto control and self control transfer instructions
d) all of the mentioned

View Answer

Answer: b [Reason:] The control transfer instructions are divided into conditional and unconditional control transfer instructions.

8. The conditional control transfer instructions check a bit condition which includes any bit of
a) bit addressable RAM
b) bit addressable SFRs
c) content of accumulator
d) all of the mentioned

View Answer

Answer: d [Reason:] The conditional control transfer instructions check a bit condition which includes any bit of bit addressable RAM or bit addressable SFRs or content of accumulator for transferring the control to the specified jump location.

9. All conditional jumps are
a) absolute jumps
b) long jumps
c) short jumps
d) none

View Answer

Answer: c [Reason:] All conditional jumps are short jumps.

10. The first byte of a short jump instruction represents
a) opcode byte
b) relative address
c) opcode field
d) none

View Answer

Answer: a [Reason:] The short jump instruction has two byte instruction. The first byte represents opcode byte and second byte represents an 8-bit relative address.

11. In logical instructions, the immediate data can be an operand for
a) increment operation
b) decrement operation
c) single operand instruction
d) none

View Answer

Answer: d [Reason:] In logical instructions, the immediate data can’t be an operand for increment/decrement or any other single operand instruction.

Interview MCQ Set 2

1. Which of the following is not a scale factor of addressing modes of 80386?
a) 2
b) 4
c) 6
d) 8

View Answer

Answer: c [Reason:] In case of the scaled the modes, any of the index register values can be multiplied by a valid scale factor to obtain the displacement. The valid scale factors are 1, 2, 4 and 8.

2. Contents of an index register are multiplied by a scale factor that may be added further to get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned

View Answer

Answer: b [Reason:] In scaled indexed mode, contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

3. Contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset in
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) none of the mentioned

View Answer

Answer: a [Reason:] In base scaled indexed mode, contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset.

4. In based scaled indexed mode with displacement mode, the contents of an index register are multiplied by a scale factor and are added to
a) base register
b) displacement
c) base register and displacement
d) none of the mentioned

View Answer

Answer: c [Reason:] Contents of an index register are multiplied by a scale factor and the result is added to a base register and a displacement to get the offset of an operand.

5. The following statement of ALP is an example of
MOV EBX, [EDX*4] [ECX].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode

View Answer

Answer: a [Reason:] Since in base scaled indexed mode, contents of an index register are multiplied by a scale factor and then added to base register to get the operand offset.

6. The following statement is an example of
MOV EBX, LIST [ESI*2].
MUL ECX, LIST [EBP*4].
a) base scaled indexed mode
b) scaled indexed mode
c) indexed mode
d) based scaled indexed mode with displacement mode

View Answer

Answer: b [Reason:] Since in scaled indexed mode, contents of an index register are multiplied by a scale factor that may be added further to get the operand offset.

7. Bit field can be defined as a group of
a) 8 bits
b) 16 bits
c) 32 bits
d) 64 bits

View Answer

Answer: c [Reason:] A group of at the most 32 bits(4 bytes) is defined as a bit field.

8. The maximum length of the string in a bit string of contiguous bits is
a) 2 MB
b) 4 MB
c) 2 GB
d) 4 GB

View Answer

Answer: d [Reason:] Bit string is a string of contiguous bits of maximum 4Gbytes in length.

9. The integer word is defined as
a) signed 8-bit data
b) unsigned 16-bit data
c) signed 16-bit data
d) signed 32-bit data

View Answer

Answer: c [Reason:] The integer word is the signed 16-bit data.

10. A 16-bit displacement that references a memory location using any of the addressing modes is
a) Pointer
b) Character
c) BCD
d) Offset

View Answer

Answer: d [Reason:] Offset is a 16-bit or 32-bit displacement that references a memory location using any of the addressing modes.

11. A decimal digit can be represented by
a) unsigned integer
b) signed integer
c) unpacked BCD
d) packed BCD

View Answer

Answer: c [Reason:] Decimal digits from 0-9 are represented by unpacked bytes.

Interview MCQ Set 3

1. Which of the following is not an addressing mode of 8051?
a) register instructions
b) register specific instructions
c) indexed addressing
d) none

View Answer

Answer: d [Reason:] The six addressing modes of 8051 are 1. Direct addressing 2. Indirect addressing 3. Register instructions 4. Register specific(Register Implicit) instructions 5. Immediate mode 6. Indexed addressing.

2. The symbol, ‘addr 16’ represents the 16-bit address which is used by the instructions to specify the
a) destination address of CALL
b) source address of JUMP
c) destination address of call or jump
d) source address of call or jump

View Answer

Answer: c [Reason:] The symbol, ‘addr 16’ represents the 16-bit destination address which is used by the LCALL or LJMP instruction to specify the call or jump destination address, within 64 Kbytes program memory.

3. The storage of addresses that can be directly accessed is
a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS

View Answer

Answer: c [Reason:] Only internal data RAM and SFRS can be directly addressed in direct addressing mode.

4. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator

View Answer

Answer: b [Reason:] The address register for storing the 16-bit addresses can only be data pointer.

5. The address register for storing the 8-bit addresses can be
a) R0 of selected bank of register
b) R1 of selected bank of register
c) Stack pointer
d) All of the mentioned

View Answer

Answer: d [Reason:] The registers R0 and R1 of the selected bank of registers or stack pointer can be used as address registers for storing the 8-bit addresses.

6. The instruction, ADD A, R7 is an example of
a) register instructions
b) register specific instructions
c) indexed addressing
d) none

View Answer

Answer: a [Reason:] In register instructions addressing mode, operands are stored in the registers R0-R7 of the selected register bank. One of these registers is specified in the instruction.

7. The addressing mode, in which the instructions has no source and destination operands is
a) register instructions
b) register specific instructions
c) direct addressing
d) indirect addressing

View Answer

Answer: b [Reason:] In register specific instructions addressing mode, the instructions donot have source and destination operands. Some of the instructions always operate only on a specific register.

8. The instruction, RLA performs
a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right

View Answer

Answer: b [Reason:] The instruction, RLA rotates accumulator left.

9. The instruction, ADD A, #100 performs
a) 100(decimal) is added to contents of address register
b) 100(decimal) is subtracted from accumulator
c) 100(decimal) is added to contents of accumulator
d) none

View Answer

Answer: c [Reason:] Immediate data 100(decimal) is added to the contents of accumulator.

10. In which of these addressing modes, a constant is specified in the instruction, after the opcode byte?
a) register instructions
b) register specific instructions
c) direct addressing
d) immediate mode

View Answer

Answer: d [Reason:] In immediate mode, an immediate data, i.e. a constant is specified in the instruction, after the opcode byte.

11. The only memory which can be accessed using indexed addressing mode is
a) RAM
b) ROM
c) Main memory
d) Program memory

View Answer

Answer: d [Reason:] Only program memory can be accessed using the indexed addressing mode.

12. The data address of look-up table is found by adding the contents of
a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer

View Answer

Answer: b [Reason:] The look-up table data address is found out by adding the contents of register accumulator with that of the program counter or data pointer.

Interview MCQ Set 4

1. The instruction, MOV AX, 0005H belongs to the address mode
a) register
b) direct
c) immediate
d) register relative

View Answer

Answer: c [Reason:] In Immediate addressing mode, immediate data is a part of instruction and appears in the form of successive byte or bytes.

2. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode

View Answer

Answer: c [Reason:] Since immediate data is present in the instruction.

3. The instruction, MOV AX, [2500H] is an example of
a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode

View Answer

Answer: b [Reason:] Since the address is directly specified in the instruction as a part of it.

4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode

View Answer

Answer: b [Reason:] Since register is used to refer the address.

5. The instruction, MOV AX,[BX] is an example of
a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode

View Answer

Answer: d [Reason:] Since the register used to refer the address is accessed indirectly.

6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned

View Answer

Answer: c [Reason:] In indexed addressing mode, the offset of operand is stored and in the rest of them, address is stored.

7. The addressing mode that is used in unconditional branch instructions is
a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode

View Answer

Answer: b [Reason:] In intrasegment indirect mode, the branch address is found as the content of a register or a memory location.

8. If the location to which the control is to be transferred lies in a different segment other than the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode

View Answer

Answer: d [Reason:] In intersegment mode, the control to be transferred lies in a different segment.

9. The instruction, JMP 5000H:2000H;
is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode

View Answer

Answer: c [Reason:] Since in intersegment direct mode, the address to which the control is to be transferred is in a different segment.

10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode

View Answer

Answer: d [Reason:] The effective address is formed by adding the contents of both base and index registers to a default segment.

Interview MCQ Set 5

1. The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register

View Answer

Answer: d [Reason:] In some instructions, the Accumulator and B register are used to store the operands.

2. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register

View Answer

Answer: b [Reason:] B register is used to store one of the operands for multiply and divide instructions. In other instructions, it may just be used as a scratch pad.

3. The registers that contains the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned

View Answer

Answer: c [Reason:] The set of flags of program status word contains the status information and is considered as one of the special function registers.

4. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386

View Answer

Answer: c [Reason:] The 8051 stack is not a top-down data structure, like other Intel processors.

5. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned

View Answer

Answer: d [Reason:] The architecture of 8051 consists of 4 latches and driver pairs are alloted to each of the four on-chip I/O ports. It contains two 16-bit timer registers.

6. The transmit buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register

View Answer

Answer: b [Reason:] The transmit buffer of serial data buffer is a parallel-in serial-out register.

7. The receive buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register

View Answer

Answer: a [Reason:] The serial data register has two buffers. The transmit buffer is a parallel-in serial-out register and receive buffer is a parallel-in serial-out register.

8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON

View Answer

Answer: b [Reason:] The registers, TMOD and TCON contain control and status information about timers/counters.

9. The register that provides control and status information about serial port is
a) IP
b) IE
c) TSCON
d) PCON and SCON

View Answer

Answer: d [Reason:] The registers, PCON and SCON contain control and status information about serial port.

10. The device that generates the basic timing clock signal for the operation of the circuit using crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator

View Answer

Answer: c [Reason:] The oscillator circuit generates the basic timing clock signal for the operation of the circuit using crystal oscillator.

11. The registers that are not accessible by the user are
a) Accumulator and B register
b) IP and IE
c) Instruction registers
d) TMP1 and TMP2

View Answer

Answer: d [Reason:] The arithmetic operations are performed over the operands held by the temporary registers, TMP1 and TMP2. Users cannot access these temporary registers.

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