Multiple choice question for engineering
Set 1
1. Modulus refers to
a) A method used to fabricate decade counter units
b) The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
c) An input on a counter that is used to set the counter state, such as UP/DOWN
d) The maximum number of states in a counter sequence
Answer
Answer: d [Reason:] Modulus is defined as the maximum number of stages/states a counter has.
2. A sequential circuit design is used to
a) Count up
b) Count down
c) Decode an end count
d) Count in a random order
Answer
Answer: d [Reason:] A sequential circuit design is used to count in a random manner which is faster than combinational circuit.
3. In general, when using a scope to troubleshoot digital systems, the instrument should be triggered by
a) The A channel or channel 1
b) The vertical input mode, when using more than one channel
c) The system clock
d) Line sync, in order to observe troublesome power line glitches
Answer
Answer: c [Reason:] All the information is sent from one end to another end through the clock pulse which behaves like a carrier. So, for troubleshooting it should be triggered by the same.
4. Which counters are often used whenever pulses are to be counted and the results displayed in decimal?
a) Synchronous
b) Bean
c) Decade
d) BCD
Answer
Answer: d [Reason:] BCD means Binary Coded Decimal, which means that decimal numbers coded of binary numbers.
5. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
a) 74134
b) LPM
c) Synchronous
d) AHDL
Answer
Answer: b [Reason:] The library of parameterized modules (LPM) counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
6. The minimum number of flip-flops that can be used to construct a modulus-5 counter is
a) 3
b) 8
c) 5
d) 10
Answer
Answer: a [Reason:] The minimum number of flip-flops used in a counter is given by: 2(n-1)<=N<=2n.
7. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is
a) 20%
b) 50%
c) 10%
d) 80%
Answer
Answer: a [Reason:] There are 10 states, out of which MSB is high only for (1000, 1001) 2 times. Hence duty cycle is 2/10*100 = 20%.
8. Normally, synchronous counter is designed using
a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
Answer
Answer: b [Reason:] Since, J-K flip-flops have options of recovery from toggle condition and by using less number of J-K flip-flops a synchronous counter can be designed. So, it is more preferred.
9. MOD-16 counter requires ________ no. of states.
a) 8
b) 4
c) 16
d) 32
Answer
Answer: c [Reason:] 2n>=2(n-1), by using this formula we get the value of N=16.
10. What is state diagram?
a) It provides the graphical representation of states
b) It provides exactly the same information as the state table
c) It is same as the truth table
d) None of the Mentioned
Answer
Answer: b [Reason:] The state diagram provides exactly the same information as the state table and is obtained directly from the state table.
11. High speed counter is
a) Ring counter
b) Ripple counter
c) Synchronous counter
d) Asynchronous counter
Answer
Answer: c [Reason:] Synchronous counter doesn’t have propagation delay.
12. Program counter in a digital computer
a) Counts the number of programs run in the machine
b) Counts the number of times a subroutine
c) Counts the number of time the loops are executed
d) Points the memory address of the current or the next instruction
Answer
Answer: d [Reason:] Program counter in a digital computer points the memory address of the current or the next instruction.
13. Fundamental mode is another name for
a) Level operation
b) Pulse operation
c) Clock operation
d) None of the Mentioned
Answer
Answer: b [Reason:] Whatever the input given to the devices are in the form of pulses always. That is why, it is known as fundamental mode.
Set 2
1. All input of NOR as low produces result as
a) Low
b) Mid
c) High
d) None of the Mentioned
Answer
Answer: c [Reason:] All input of NOR as low produces result as high.
2. In RTL NOR gate, the output is at logic 1 only when all the inputs are at
a) logic 0
b) logic 1
c) +10v
d) None of the Mentioned
Answer
Answer: a [Reason:] RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the inputs are at logic 0.
3. Resistor–transistor logic (RTL) is a class of digital circuits built using _______ as the input network and _______ as switching devices.
a) Resistors, bipolar junction transistors (BJTs)
b) Bipolar junction transistors (BJTs), Resistors
c) Capacitors, resistors
d) Resistors, capacitors
Answer
Answer: a [Reason:] Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the input network and bipolar junction transistors (BJTs) as switching devices.
4. RTL consists of a common emitter stage with a _______ connected between the base and the input voltage source.
a) collector
b) base resistor
c) Capacitor
d) None of the Mentioned
Answer
Answer: b [Reason:] RTL consist of a common emitter stage with a base resistor connected between the base and the input voltage source. The role of base resistor is to expand the negligible transistor input voltage range (about 0.7 V) to the logical “1” level (about 3.5 V) by converting the input voltage into current.
5. The role of the _______ is to convert the collector current into voltage in RTL.
a) Collector resistor
b) Base resistor
c) Common emitter
d) Transistor
Answer
Answer: a [Reason:] The role of the collector resistor is to convert the collector current into voltage; its resistance is chosen high enough to saturate the transistor and low enough to obtain low output resistance.
6. The limitations of the one transistor RTL NOR gate are overcome by
a) Two-transistor RTL implementation
b) Three-transistor RTL implementation
c) Multi-transistor RTL implementation
d) None of the Mentioned
Answer
Answer: c [Reason:] The limitations of the one transistor RTL NOR gate are overcome by the use of multi transistor RTL. It consists of a set of parallel connected transistor switches driven by the logic inputs.
7. The primary advantage of RTL technology was that
a) It results as low power dissipation
b) It uses a minimum number of resistors
c) It uses a minimum number of transistors
d) None of the Mentioned
Answer
Answer: c [Reason:] The primary advantage of RTL technology was that it uses a minimum number of transistors. It consist of registers in large amount and it results as high power dissipation.
8. The disadvantage of RTL is that
a) It uses a maximum number of resistors
b) It results in high power dissipation
c) High noise creation
d) None of the Mentioned
Answer
Answer: b [Reason:] The disadvantage of RTL is its high power dissipation when the transistor is switched on by current flowing in the collector and base resistor. This requires that more current be supplied to and heat be removed from RTL circuits. In contrast TTL circuits with “totem-pole” output stage minimize both of these requirements.
9. TTL circuits with “totem-pole” output stage minimize
a) The power dissipation in RTL
b) The time consumption in RTL
c) The speed of transferring rate in RTL
d) Nothing
Answer
Answer: a [Reason:] TTL circuits with “totem-pole” output stage minimize the power dissipation and heating effect in RTL.
10. The minimum number of transistors can be used by 2 input AND gate is
a) 2
b) 3
c) 4
d) 5
Answer
Answer: a [Reason:] The minimum number of transistors can be used by 2 input AND gate is 2 and maximum upto 3.
Set 3
1. A register is defined as
a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
Answer
Answer: d [Reason:] A register is defined as the group of flip-flops suitable for storing binary information. Each flip-flop is a binary cell capable of storing one bit of information.
2. The register is a type of
a) Combinational circuit
b) Sequential circuit
c) CPU
d) Latches
Answer
Answer: a [Reason:] Register’s output depends on the order or timing of the inputs. The device who follows this properties is termed as sequential circuit.
3. How many types of registers are?
a) 2
b) 3
c) 4
d) 5
Answer
Answer: c [Reason:] There are 4 types of registers, viz., S-R, J-K, D, & T register.
4. The main difference between a register and a counter is
a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) None of the Mentioned
Answer
Answer: a [Reason:] The main difference between a register and a counter is that a register has no specific sequence of states except in certain specialised applications.
5. In D register, ‘D’ stands for
a) Delay
b) Decrement
c) Data
d) Decay
Answer
Answer: c [Reason:] D stands for data in case of register not delay.
6. Registers capable of shifting in one direction is
a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
Answer
Answer: b [Reason:] The register capable of shifting in one direction is unidirectional shift register.
7. A register that is used to store binary information is called
a) Data register
b) Binary register
c) Shift register
d) None of the Mentioned
Answer
Answer: b [Reason:] A register that is used to store binary information is called binary register.
8. A shift register is defined as
a) The register capable of shifting an information to another register
b) The register capable of shifting an information either to the right or to the left
c) The register capable of shifting an information to the right only
d) The register capable of shifting an information to the left only
Answer
Answer: b [Reason:] The register capable of shifting an information either to the right or to the left is termed as shift register.
9. How many methods of shifting of data are available?
a) 2
b) 3
c) 4
d) 5
Answer
Answer: a [Reason:] There are two types of shifting of data are available and these are serial shifting & parallel shifting.
10. In serial shifting method, data shifting occurs
a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
Answer
Answer: a [Reason:] As the name suggests serial shifting, it means that data shifting will take place one bit at a time for each clock pulse in a serial fashion.
Set 4
1. Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.
a) 2
b) 3
c) 4
d) 5
Answer
Answer: c [Reason:] Based on how binary information is entered or shifted out, shift registers are classified into 4 categories, viz., SISO, SIPO, PISO, PIPO.
2. The full form of SIPO is
a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) None of the Mentioned
Answer
Answer: a [Reason:] SIPO is always known as Serial-in Parallel-out.
3. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Answer
Answer: c [Reason:] The universal register is capable of shifting left, right and parallel load capabilities.
4. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Answer
Answer: d [Reason:] Because no other flip-flops are connected with the output Q.
5. What is meant by parallel load of a shift register?
a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) None of the Mentioned
Answer
Answer: a [Reason:] At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is definitely 1.
6. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________
a) 01110
b) 00001
c) 00101
d) 00110
Answer
Answer: c [Reason:] LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.
7. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
Answer
Answer: c [Reason:] Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
8. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
Answer
Answer: c [Reason:] Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
9. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Answer
Answer: b [Reason:] f = 200 KHZ; T = (1/200) m sec; T = (1/0.2) micro-sec; T = 5 micro-sec; After 8 clock cycles only 8 bit will be loaded = 8 * 5 = 40 micro-sec.
10. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________
a) 16 s
b) 8 s
c) 4 s
d) 2 s
Answer
Answer: c [Reason:] One clock period is .5 microseconds. So, the total delay of .5*8, i.e. 4 micro seconds time is required to transmit information of 8 bits.
Set 5
1. The logical sum of two or more logical product terms is called
a) SOP
b) POS
c) OR operation
d) NAND operation
Answer
Answer: a [Reason:] The logical sum of two or more logical product terms, is called SOP (i.e. sum of product).
2. The expression Y=AB+BC+AC shows the _________ operation.
a) EX-OR
b) SOP
c) POS
d) NOR
Answer
Answer: b [Reason:] The given expression has the operation product as well as the sum of that. So, it shows SOP operation.
3. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.
a) AND
b) POS
c) SOP
d) NAND
Answer
Answer: b [Reason:] The given expression has the operation sum as well as the product of that. So, it shows POS(product of sum) operation.
4. A product term containing all K variables of the function in either complemented or uncomplemented form is called a
a) Minterm
b) Maxterm
c) Midterm
d) None of the Mentioned
Answer
Answer: a [Reason:] A product term containing all K variables of the function in either complemented or uncomplemented form is called a minterm.
5. According to the property of minterm, how many combination will have value equal to 1 for K input variables?
a) 0
b) 1
c) 2
d) 3
Answer
Answer: b [Reason:] The main property of a minterm is that it possesses the value 1 for only one combination of K input variables and the remaining will have the value 0.
6. The canonical sum of product form of the function y(A,B) = A + B is
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) None of the Mentioned
Answer
Answer: b [Reason:] A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’ + A’B = AB + AB’ + A’B.
7. A variable on its own or in its complemented form is known as a
a) Product Term
b) Literal
c) Sum Term
d) None of the Mentioned
Answer
Answer: b [Reason:] A literal is a single logic variable or its complement. For example — X, Y, A’, Z, X’ etc.
8. Maxterm is the sum of __________of the corresponding Minterm with its literal complemented.
a) Terms
b) Words
c) Numbers
d) None of the Mentioned
Answer
Answer: a [Reason:] Maxterm is the sum of terms of the corresponding Minterm with its literal complemented.
9. Canonical form is a unique way of representing________________
a) SOP
b) Minterm
c) Boolean Expressions
d) A page
Answer
Answer: c [Reason:] Boolean Expressions are represented through canonical form. An example of canonical form is A’B’C’ + AB’C + ABC’.
10. There are _____________ Minterms for 3 variables (a, b, c).
a) 0
b) 2
c) 8
d) None of the Mentioned
Answer
Answer: c [Reason:] Minterm is given by 2^n. So, 2^3 = 8 minterms are required.
11. _____________ expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) None of the Mentioned
Answer
Answer: c [Reason:] SOP expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-level NAND logic circuits.