Multiple choice question for engineering
Set 1
1. A latch is an example of a
a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) None of the Mentioned
Answer
Answer: c [Reason:] A latch is an example of a bistable multivibrator. bistable multivibrator, in which the circuit is stable in either state. It can be flipped from one state to the other state.
2. Latch is a device with
a) One stable state
b) Two stable state
c) Three stable state
d) None of the Mentioned
Answer
Answer: b [Reason:] Since, a latch works on the principal of bistable multivibrator. So, it has two stable states.
3. Why latches are called a memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) None of the Mentioned
Answer
Answer: c [Reason:] Latches can be memory devices, and can store one bit of data for as long as the device is powered.
4. Two stable states of latches are
a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
Answer
Answer: c [Reason:] There are two stable states of latches and these states are high-output and low-output.
5. How many types of latches are
a) 2
b) 3
c) 4
d) 5
Answer
Answer: a [Reason:] There are two types of latches: SR latch & D latch.
6. The full form of SR is
a) System rated
b) Set reset
c) Set ready
d) None of the Mentioned
Answer
Answer: b [Reason:] The full form of SR is set/reset.
7. The SR latch consists of
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
Answer
Answer: b [Reason:] The diagram of SR latch is shown below:
8. The outputs of SR latch are
a) x and y
b) a and b
c) s and r
d) q and q’
Answer
Answer: d [Reason:] The outputs of SR latch are q and q’. It is clear from the diagram:
.
9. The NAND latch works when both inputs are
a) 1
b) 0
c) Inverted
d) Don’t cares
Answer
Answer: a [Reason:] The NAND latch works when both inputs are 1. Since, both of the inputs are inverted in a NAND latch.
10. The first step of analysis procedure of SR latch is to
a) label inputs
b) label outputs
c) label states
d) label tables
Answer
Answer: b [Reason:] All flip flops have at least one output labeled Q (i.e. inverted).
11. The inputs of SR latch are
a) x and y
b) a and b
c) s and r
d) j and k
Answer
Answer: c [Reason:] The inputs of SR latch are s and r.
12. When a high is applied to the Set line of an SR latch, then
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) None of the Mentioned
Answer
Answer: a [Reason:] S input of a SR latch is directly connected to the output Q. So, when a high is applied Q output goes high and Q’ low.
13. When both inputs of SR latches are low, the latch
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Answer
Answer: c [Reason:] When both inputs of SR latches are low, the latch remains in its previously set or reset state.
14. When both inputs of SR latches are high, the latch goes
a) Unstable
b) Stable
c) Metastable
d) None of the Mentioned
Answer
Answer: c [Reason:] When both gates are identical and this is “metastable”, and the device will be in an undefined state for an indefinite period.
Set 2
1. The full form of LCD is
a) LIquid Crystal Display
b) Liquid Crystalline Display
c) Logical Crystal Display
d) Logical Crystalline Display
Answer
Answer: a [Reason:] The full form of LCD is “LIquid Crystal Display”.
2. The optical properties of liquid crystals depend on the direction of
a) Air
b) Solid
c) Light
d) Water
Answer
Answer: c [Reason:] The optical properties of liquid crystals depend on the direction of light travels through a layer of the material.
3. By which properties, the orientation of molecules in a layer of liquid crystals can be changed?
a) Magnetic field
b) Electric field
c) Electromagnetic field
d) None of the Mentioned
Answer
Answer: b [Reason:] In LCD, the electric field is induced by a small electric voltage applied across it; Due to which the orientation of molecules in a layer of liquid crystals can be changed.
4. Electro-optical effect is produced in
a) LED
b) LCD
c) OFC
d) None of the Mentioned
Answer
Answer: b [Reason:] An electric field (induced by a small electric voltage) can change the orientation of molecules in a layer of liquid crystal and thus affect its optical properties. Such a process is termed an electro-optical effect, and it forms the basis for LCDs.
5. The direction of electric field in a LCD is determined by
a) the molecule’s chemical structure
b) Crystalline surface structure
c) Molecular Orbital Theory
d) None of the Mentioned
Answer
Answer: a [Reason:] For LCDs, the change in optical properties results from orienting the molecular axes either along or perpendicular to the applied electric field, the preferred direction being determined by the details of the molecule’s chemical structure.
6. The first LCDs became commercially available in
a) 1950s
b) 1980s
c) 1960s
d) None of the Mentioned
Answer
Answer: c [Reason:] The first LCDs became commercially available in the late 1960s and were based on a light-scattering effect known as the dynamic scattering mode.
7. LCDs operate from a voltage ranges from
a) 3 to 15V
b) 10 to 15V
c) 10V
d) 5V
Answer
Answer: a [Reason:] LCDs operate from a voltage ranges from 3 to 15V rms.
8. LCDs operate from a frequency ranges from
a) 10Hz to 60Hz
b) 50Hz to 70Hz
c) 30Hz to 60Hz
d) None of the Mentioned
Answer
Answer: c [Reason:] LCDs operate from a frequency ranges from 30Hz to 60Hz.
9. In 7 segment display, how many LEDs are used?
a) 8
b) 7
c) 10
d) 9
Answer
Answer: b [Reason:] There are 7 LEDs used in a 7 segment display.
10. What is backplane in LCD?
a) The ac voltage applied between segment and a common element
b) The dc voltage applied between segment and a common element
c) The amount of power consumed
d) None of the Mentioned
Answer
Answer: a [Reason:] The ac voltage applied between segment and a common element is called the backplane(bp). In which each segment is driven by an EX-OR gate.
Set 3
1. The output of a logic gate is 1 when all the input are at logic 0 as shown below:
| INPUT | OUTPUT | |
|---|---|---|
| A | B | C |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
| INPUT | OUTPUT | |
|---|---|---|
| A | B | C |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The gate is either
a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Answer
Answer: d [Reason:] The output of a logic gate is 1 when all inputs are at logic 0. The gate is either a NOR or an EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in above figure.)
2. The code where all successive numbers differ from their preceding number by single bit is
a) Binary code
b) BCD
c) Excess 3
d) Gray
Answer
Answer: d [Reason:] The code where all successive numbers differ from their preceding number by single bit is gray code. It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next.
3. The following switching functions are to be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Answer
Answer: c [Reason:] 4 to 16 line decoder as the minterms are ranging from 1 to 14.
4. How many AND gates are required to realize Y = CD + EF + G ?
a) 4
b) 5
c) 3
d) 2
Answer
Answer: d [Reason:] To realize Y = CD + EF + G, two AND gates are required.
5. The NOR gate output will be high if the two inputs are
a) 00
b) 01
c) 10
d) 11
Answer
Answer: a [Reason:] In option b, c or d output is low if any of the I/P is high. So, the correct option will be a.
6. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) None of the Mentioned
Answer
Answer: a [Reason:] Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.
7. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Answer
Answer: d [Reason:] NAND can generate any logic function.
8. A full adder logic circuit will have
a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Answer
Answer: d [Reason:] A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
9. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 1, 1
b) 4, 2
c) 3, 2
d) 2, 3
Answer
Answer: a [Reason:] There are three product terms. So, three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
10. Which of following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) None of the Mentioned
Answer
Answer: a [Reason:] The NAND & NOR gates are known as universal gates because any digital circuit can be realized completely by using either of these two gates.
11. The gates required to build a half adder are
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) Four NAND gates
Answer
Answer: c [Reason:] The gates required to build a half adder are EX-OR gate and AND gate.
Set 4
1. All the comparisons made by comparator is done using
a) 1 circuit
b) 2 circuits
c) 3 circuits
d) 4 circuits
Answer
Answer: a [Reason:] Because, all of the output is compared with each other and it is possible only by using 1 circuit.
2. One that is not the outcome of magnitude comparator is
a) a > b
b) a – b
c) a < b
d) a = b
Answer
Answer: c [Reason:] In a digital comparator, only 3 outputs are possible (i.e. A = B, A> B, A < B). So, a < b is incorrect option.
3. If two numbers are not equal then binary variable will be
a) 0
b) 1
c) a
d) b
Answer
Answer: a [Reason:] In a digital comparator, only 3 outputs are possible (i.e. A = B, A >B, A < B). Other than this, the output will be 0.
4. How many inputs are required for a digital comparator?
a) 1
b) 2
c) 3
d) 4
Answer
Answer: a [Reason:] There are two inputs required for a digital comparator (i.e. A & B).
5. In a comparator, if we get input as A>B then the output will be
a) 1
b) 0
c) A
d) B
Answer
Answer: a [Reason:] If A > B, it means that it satisfies one of the condition among three. Hence the output will be 1.
6. Which one is a basic comparator?
a) XOR
b) XNOR
c) AND
d) NAND
Answer
Answer: a [Reason:] A XNOR gate is a basic comparator, because its output is “1” only if its two input bits are equal.
7. Comparators are used in
a) Memory
b) CPU
c) Motherboard
d) Hard drive
Answer
Answer: b [Reason:] Comparators are used in central processing unit (CPUs). Because, all the arithmetic and logical operations are performed in the CPU.
8. A circuit that compares two numbers and determine their magnitude is called
a) Height comparator
b) Size comparator
c) Comparator
d) Magnitude comparator
Answer
Answer: d [Reason:] A circuit that compares two numbers and determine their magnitude is called magnitude comparator.
9. A procedure that specifies finite set of steps is called
a) Algorithm
b) Flow chart
c) Chart
d) Venn diagram
Answer
Answer: a [Reason:] A procedure that specifies finite set of steps is called algorithm.
10. How many types of digital comparators are?
a) 1
b) 2
c) 3
d) 4
Answer
Answer: b [Reason:] There are two main types of Digital Comparator available and these are: Identity Comparator & Magnitude Comparator.
11. An identify comparator is defined as a digital comparator which has
a) Only one output terminal
b) Two output terminals
c) Three output terminals
d) None of the Mentioned
Answer
Answer: a [Reason:] An Identity Comparator is a digital comparator that has only one output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0.
12. A magnitude comparator is defined as a digital comparator which has
a) Only one output terminal
b) Two output terminals
c) Three output terminals
d) None of the Mentioned
Answer
Answer: c [Reason:] A Magnitude Comparator is a digital comparator which has three output terminals, one each for equality, A = B greater than, A > B and less than A < B.
13. The purpose of a Digital Comparator is
a) To convert analog input into digital
b) To create different outputs
c) To add a set of different numbers
d) To compare a set of variables or unknown numbers
Answer
Answer: d [Reason:] The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such as B (B1, B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result of the comparison.
14. TTL 74LS85 is a
a) 1-bit digital comparator
b) 4-bit magnitude comparator
c) 8-bit magnitude comparator
d) 8-bit word comparator
Answer
Answer: b [Reason:] TTL 74LS85 is a 4-bit magnitude comparator.
Set 5
1. The full form of MOS is
a) Metal oxide semiconductor
b) Metal oxygen semiconductor
c) Metallic oxide semiconductor
d) Metallic oxygen semiconductor
Answer
Answer: a [Reason:] The full form of MOS is “Metal Oxide Semiconductor”.
2. What are the types of MOSFET devices available?
a) P-type enhancement type MOSFET
b) N-type enhancement type MOSFET
c) Depletion type MOSFET
d) All of the mentioned
Answer
Answer: d [Reason:] MOSFET are of two types: enhancement and depletion type. Further, these are classified into n-type and p-type device.
3. Which insulating layer used in fabrication of MOSFET?
a) Aluminium oxide
b) Silicon Nitride
c) Silicon dioxide
d) None of the mentioned
Answer
Answer: c [Reason:] Silicon dioxide is used as insulating layer in fabrication of MOSFET. It gives an extremely high input resistance in the order of 10^10 to 10^15 Ω for MOSFET.
4. Which of the following plays an important role in improving device performance of MOSFET?
a) Dielectric constant
b) Threshold voltage
c) Power supply voltage
d) Gate to drain voltage
Answer
Answer: b [Reason:] In MOSFET, the threshold voltage is typically 3 to 6V. This large voltage is not compatible with the supply of 5V which is used in digital ICs. So, for the improvement of the device’s performance the magnitude of threshold voltage should be reduced.
5. A technique used to reduce the magnitude of threshold voltage of MOSFET is the
a) Use of complementary MOSFET
b) Use of Silicon nitride
c) Using thin film technology
d) None of the mentioned
Answer
Answer: b [Reason:] Silicon nitride is sandwiched between two SiO2 layer and provide necessary barrier. The dielectric constant of Si3N4 is 7.5, whereas that of SiO2 is 4. This increase in overall dielectric constant reduces threshold voltage.
6. What is used to higher the speed of operation in MOSFET fabrication?
a) Ceramic gate
b) Silicon dioxide
c) Silicon nitride
d) Poly silicon gate
Answer
Answer: d [Reason:] In conventional metal gate small overlap capacitance is present, which lowers the speed of operation. With the presence of self aligning property of the poly silicon gate it eliminates this capacitance.
7. Find the sequence of steps involved in fabrication of poly silicon gate MOSFET?
Step 1: Entire wafer surface of a Si3N4 is coated and is etched away with the help of mask to include source, gate and drain.
Step 2: The contact areas are defined using photolithographic process.
Step 3: Selective etching of Si3N4 and growth of thin oxide.
Step 4: The deposition of poly silicon gate.
Step 5: The growth of thick oxide is called field oxide and P implantation.
Step 6: The metallization and interconnection between substrate and source.
a) 1->5->3->4->2->6
b) 1->3->4->2->5->6
c) 1->5->4->3->2->6
d) 1->4->2->5->3->6
Answer
Answer: a [Reason:] These steps are the sequence of steps involved in fabrication of poly silicon gate MOSFET.
8. Why MOSFET is preferred over BJT in IC components?
a) MOSFET has low packing density
b) MOSFET has medium packing density
c) MOSFET has high packing density
d) MOSFET has no packing density
Answer
Answer: a [Reason:] There are two additional steps required in the formation of p-mos transistor as compared to n-mos transistor. These are the formation of n-region and ion implantation of p-type source and drain regions.
9. Critical defects per unit chip area is ________ for a MOS transistor.
a) High
b) Low
c) Neutral
d) Unpredictable
Answer
Answer: b [Reason:] Critical defects per unit chip area is low for a MOS transistor because it involves fewer steps in the fabrication of a MOS transistor.
10. MOS is being used in
a) LSI
b) VLSI
c) MSI
d) Both LSI and VLSI
Answer
Answer: d [Reason:] Since, more transistor and circuitry functions can be achieved on a single chip with MOS technology that is why MOS is being used in LSI and VLSI.