Multiple choice question for engineering
Set 1
1. Which of the following allows a lower priority task to run despite the higher priority task is active and waiting to preempt?
a) message queue
b) message passing
c) semaphore
d) priority inversion
Answer
Answer: d [Reason:] The priority inversion mechanism where the lower priority task can continue to run despite there being a higher priority task active and waiting to preempt.
2. What happens to the interrupts in an interrupt service routine?
a) disable interrupt
b) enable interrupts
c) remains unchanged
d) ready state
Answer
Answer: a [Reason:] In the interrupt service routine, all the other interrupts are disabled till the routine completes which can cause a problem if another interrupt is received and held pending. This can result in priority inversion.
3. Which of the following is a part of RTOS kernel?
a) memory
b) input
c) ISR
d) register
Answer
Answer: c [Reason:] The ISR can send the message for the tasks and it is a part of RTOS kernel.
4. Which of the following is an industrial interconnection bus?
a) bus interface unit
b) data bus
c) address bus
d) VMEbus
Answer
Answer: d [Reason:] The VMEbus is an interconnection bus which is used in the industrial control and many other real-time applications.
5. Which of the following supports seven interrupt priority level?
a) kernel
b) operating system
c) VMEbus
d) data bus
Answer
Answer: c [Reason:] The VMEbus supports seven interrupt priority level which allows the prioritisation of the resources.
6. What type of interrupt handling is seen in multiprocessor applications?
a) centralised interrupt
b) handled by one MASTER
c) distributed handling
d) shared handling
Answer
Answer: c [Reason:] The multiprocessor applications allows distributed handling in which the direct communication with the individual masters is possible.
7. Which of the following is an asynchronous bus?
a) VMEbus
b) timer
c) data bus
d) address bus
Answer
Answer: a [Reason:] The VMEbus is based on Eurocard sizes and is asynchronous which is similar to the MC68000.
8. Which of the following is not a priority based?
a) priority inversion
b) message passing
c) fairness system
d) message queuing
Answer
Answer: c [Reason:] The fairness system allows the system which requires different characteristics from those originally provided and the system response that is not a priority based. The fairness system is not a priority based where the bus access is distributed across the requesting processors.
Set 2
1. Which one of the following offers CPUs as integrated memory or peripheral interfaces?
a) Microcontroller
b) Microprocessor
c) Embedded system
d) Memory system
Answer
Answer: a [Reason:] Microcontrollers are the CPUs which have integrated memory and peripherals but microprocessor possesses external chips for memory.
2. Which of the following offers external chips for memory and peripheral interface circuits?
a) Microcontroller
b) Microprocessor
c) Peripheral system
d) Embedded system
Answer
Answer: b [Reason:] Microcontrollers are the CPUs which have integrated memory and peripherals whereas microprocessor offers external chips for memory.
3. How many bits does an MC6800 family have?
a) 16
b) 32
c) 4
d) 8
Answer
Answer: d [Reason:] MC6800 is an 8-bit processor proposed by Motorola.
4. Which of the following is a 4-bit architecture?
a) MC6800
b) 8086
c) 80386
d) National COP series
Answer
Answer: d [Reason:] National COP series is a 4-bit processor whereas MC6800 is an 8-bit processor, 8086 is a 16-bit processor and 80386 is a 32-bit processor.
5. What is CISC?
a) Computing instruction set complex
b) Complex instruction set computing
c) Complementary instruction set computing
d) Complex instruction set complementary
Answer
Answer: b [Reason:] It is complementary to RISC architecture and has complex instruction set compared to RISC architecture.
6. How is the protection and security for an embedded system made?
a) OTP
b) IPR
c) Memory disk security
d) Security chips
Answer
Answer: b [Reason:] Intellectual property right provides security and protection to embedded systems.
7. Which of the following possesses a CISC architecture?
a) MC68020
b) ARC
c) Atmel AVR
d) Blackfin
Answer
Answer: a [Reason:] MC68020 is having a CISC architecture. CISC architecture is used for code efficiency whereas RISC architecture is used for speeding up the processor. ARC, Atmel AVR, and Blackfin are RISC architectures.
8. Which of the following is an RISC architecture?
a) 80286
b) MIPS
c) Zilog Z80
d) 80386
Answer
Answer: b [Reason:] MIPS possess an RISC architecture whereas 80386, 80286 and Zilog Z80 are CISC architectures.
9. Which one of the following is board based system?
a) Data bus
b) Address bus
c) VMEbus
d) DMA bus
Answer
Answer: c [Reason:] VMEbus is Versa module Europa Bus which is used as board based system for easy manipulation. VMEbus is a computer bus standard developed for Motorola MC6800 family and is mainly based on Eurocard sizes.
10. VME bus stands for
a) Versa module Europa bus
b) Versa module embedded bus
c) Vertical module embedded bus
d) Vertical module Europa bus
Answer
Answer: a [Reason:] A computer bus standard in Eurocard sizes mainly developed for Motorola MC6800 family and later on used in many applications and approved by IEEE.
Set 3
1. Which can provide efficient downloading and debugging communication between the host and target system?
a) pSOS+
b) pSOS+ kernel
c) pHILE+ file system
d) pNA+ network manager
Answer
Answer: d [Reason:] The pNA+ network manager can provide efficient downloading and debugging communication between the host and target system.
2. Which of the following is a system level debugger which provides the low-level debugging facilities and the system debugging?
a) pROBE+ system level debugger
b) pNA+ network manager
c) pHILE+ file system
d) pNA+ network manager
Answer
Answer: a [Reason:] The pROBE+ system level debugger which can provide the system debugging and the low level debugging.
3. How is the pROBE+ system level debugger communicate with the outside world?
a) peripheral output
b) serial port
c) LCD display
d) LED
Answer
Answer: b [Reason:] The pROBE+ system level debugger can communicate with the outside world through the serial port or by installing pNA+, a TCP/IP link can be used instead.
4. Which of the following is a complementary product to pROBE+ system level debugger?
a) pSOS+ kernel
b) pSOS+
c) XRAY+ source level debugger
d) pSOS+m
Answer
Answer: c [Reason:] The XRAY+ source level debugger is a complementary product to pROBE+ system level debugger as it can use the debugger information and combine with the C source and other functions on the host that can provide an integrated debugging.
5. Which of the following supports the MS-DOS file?
a) pNA+ network manager
b) pSOS+ kernel
c) pSOS+ m
d) pHILE+ file system
Answer
Answer: d [Reason:] The pHILE+ file system supports the MS-DOS file structure and the product can provide input and output file.
6. Who developed the OS-9?
a) Microwave
b) Microwave and Motorola
c) Motorola and IBM
d) Microwave and IBM
Answer
Answer: b [Reason:] The OS-9 is developed by Motorola and Microwave as a real-time operating system. The operating system is developed for MC6809 which is an 8-bit processor.
7. Who had developed VRTX-32?
a) Microtec Research
b) Microwave
c) Motorola
d) IBM
Answer
Answer: a [Reason:] The VRTX-32 is developed by Microtec Research which is a high-performance real-time kernel.
8. Which provides the library interface to allow C programs to call standard I/O functions?
a) RTL
b) TNX
c) IFX
d) MPV
Answer
Answer: a [Reason:] The RTL is a run-time library support for Microtec and the Sun compilers and can provide the library interface to allow the C programs to call the standard I/O functions.
Set 4
1. Which of the following unit protects the memory?
a) bus interface unit
b) execution unit
c) memory management unit
d) peripheral unit
Answer
Answer: c [Reason:] The resources have to be protected in an embedded system and the most important resource to be protected is the memory which is protected by the memory management unit through different programming.
2. Which unit protects the hardware?
a) MMU
b) hardware unit
c) bus interface unit
d) execution unit
Answer
Answer: a [Reason:] The hardware part are protected by the memory management unit. The memory part is also protected by the memory management unit.The hardware such as the input-output devices are protected and is prevented from the direct access.
3. Which mechanism can control the access?
a) in-situ
b) spin-lock
c) ex-situ
d) both in-situ and ex-situ
Answer
Answer: b [Reason:] Both the memory and the hardware part are protected by the memory management unit and the hardware such as the input-output devices are protected, These are prevented from the direct access. These accesses are made through a device driver and this device driver can control the serial port. Such a mechanism is called spin-lock mechanism which provides the control access.
4. Which of the following is very resilient to the system crashes?
a) Windows 3.1
b) MS-DOS
c) Windows NT
d) kernel
Answer
Answer: c [Reason:] The Windows NT is very resilient to the system crashes and the system will continue while the processes can crash. This is because of the user mode and the kernel mode which is coupled with the resource protection. This resilience is a big advantage over the MS-DOS and the Windows 3.1.
5. Which of the following are coupled in the Windows NT for the resource protection?
a) kernel mode and user mode
b) user mode and protected mode
c) protected mode and real mode
d) virtual mode and kernel mode
Answer
Answer: a [Reason:] The user mode and the kernel mode are coupled with the resource protection and this resilience in Windows NT is a big advantage over the MS-DOS and the Windows 3.1.
6. Which of the following support multi-threaded software?
a) Windows NT
b) thread
c) process
d) task
Answer
Answer: a [Reason:] The Windows NT supports multi-threaded software in which the processes can support several independent paths or threads.
7. Which provides a 4 Gbyte virtual address space?
a) Windows 3.1
b) MS-DOS
c) pSOS+
d) Windows NT
Answer
Answer: d [Reason:] The virtual address spacing in the Windows NT is somewhat different from the MS-DOS and the Windows 3.1. The Windows NT provides 4 Gbytes virtual address space for each process and that is linearly addressed using 32-bit address values.
8. Which applications can be used with the Windows NT?
a) WIN16
b) WIN32
c) WIN4
d) WIN24
Answer
Answer: b [Reason:] The WIN32 is also known as 32-bit or even native. It is used for the Windows NT applications which uses the same instruction set as that of the Windows NT and therefore do not need to emulate a different architecture.
9. Which of the following has the same instruction set as that of the Windows NT?
a) WIN32
b) WIN4
c) WIN24
d) WIN16
Answer
Answer: a [Reason:] WIN32 is used for the Windows NT applications and is also known as even native which uses the same instruction set as that of the Windows NT and therefore do not need to emulate a different architecture.
10. Which can provide more memory than the physical memory?
a) real memory
b) physical address
c) virtual memory
d) segmented address
Answer
Answer: c [Reason:] The physical memory can provide more memory than the physical memory within the system. Such memories are divided into segments and pages.
Set 5
1. What does MSR stand for?
a) machine state register
b) machine software register
c) minimum state register
d) maximum state register
Answer
Answer: a [Reason:] The MSR is a machine state register. When the exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers while handling an exception.
2. How many supervisor registers are associated with the exception mode?
a) 2
b) 3
c) 4
d) 5
Answer
Answer: a [Reason:] When the exception is recognised, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.
3. What happens when an exception is completed?
a) TRAP instruction executes
b) SWI instruction executes
c) RFI instruction executes
d) terminal count increases
Answer
Answer: c [Reason:] When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the processor moves to the supervisor mode and starts to execute the handler which is associated with the vector table. The handler examines the DSISR and FPSCR registers and carries out the required function. When it gets completed the RFI or return-from-interrupt instruction is executed.
4. How many general types of exceptions are there?
a) 2
b) 3
c) 6
d) 4
Answer
Answer: d [Reason:] There are four general types of exceptions. They are synchronous precise, asynchronous precise, synchronous imprecise and asynchronous imprecise.
5. In which of the exceptions does the external event causes the exception?
a) synchronous exception
b) asynchronous exception
c) precise
d) imprecise
Answer
Answer: b [Reason:] The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.
6. Which of the exceptions are usually a catastrophic failure?
a) imprecise exception
b) precise exception
c) synchronous exception
d) asynchronous exception
Answer
Answer: a [Reason:] An imprecise exception is a catastrophic failure in which the processor cannot continue processing or allow a particular task or program to continue.
7. Which of the exceptions allows the system reset or memory fault?
a) imprecise exception
b) precise exception
c) synchronous exception
d) asynchronous exception
Answer
Answer: a [Reason:] The system reset or memory fault falls into the category of imprecise exceptions while accessing the vector table.
8. Which registers are used to determine the completion status?
a) MSR
b) flag register
c) DSISR
d) index register
Answer
Answer: c [Reason:] The completion status can be determined by the information bits in the DSISR and FPSCR registers.
9. Which of the following does not support PowerPC architecture?
a) synchronous precise
b) asynchronous precise
c) synchronous imprecise
d) asynchronous imprecise
Answer
Answer: c [Reason:] The synchronous imprecise is usually not supported on the PowerPC architecture and also in the MPC601, MPC603 etc.
10. Which exceptions are used in the PowerPC for floating point?
a) synchronous imprecise
b) asynchronous imprecise
c) synchronous precise
d) synchronous imprecise
Answer
Answer: a [Reason:] . The PowerPC can handle the floating point exception by making use of the synchronous imprecise mode.
11. Which exception is used in the external interrupts and decrementer-caused exceptions?
a) synchronous precise
b) asynchronous precise
c) synchronous imprecise
d) asynchronous imprecise
Answer
Answer: b [Reason:] The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can occur at any time within the instruction flow.
12. Which exception can be masked by clearing the EE bit to zero in the MSR?
a) synchronous imprecise
b) synchronous precise
c) asynchronous imprecise
d) asynchronous precise
Answer
Answer: d [Reason:] The asynchronous precise type exceptions can be masked by clearing the EE bits in the MSR. This bit is automatically cleared to zero in the MSR in order to prevent this interrupt causing an exception while other exceptions are being processed.
