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Multiple choice question for engineering

Set 1

1. Which are the processors based on RISC?
a) SPARC
b) 80386
c) MC68030
d) MC68020

View Answer

Answer: a [Reason:] SPARC and MIPS processors are the first generation processors of RISC architecture.

2. What is 80/20 rule?
a) 80% instruction is generated and 20% instruction is executed
b) 80% instruction is executed and 20% instruction is generated
c) 80%instruction is executed and 20% instruction is not executed
d) 80% instruction is generated and 20% instructions are not generated

View Answer

Answer: a [Reason:] 80% of instructions are generated and only 20% of the instruction set is executed that is, by simplifying the instructions, the performance of the processor can be increased which lead to the formation of RISC that is reduced instruction set computing.

3. Which of the architecture is more complex?
a) SPARC
b) MC68030
c) MC68030
d) 8086

View Answer

Answer: a [Reason:] SPARC have RISC architecture which has a simple instruction set but MC68020, MC68030, 8086 have CISC architecture which is more complex than CISC.

4. Which is the first company who defined RISC architecture?
a) Intel
b) IBM
c) Motorola
d) MIPS

View Answer

Answer: b [Reason:] In 1970s IBM identified RISC architecture.

5. Which of the following processors execute its instruction in a single cycle?
a) 8086
b) 8088
c) 8087
d) MIPS R2000

View Answer

Answer: d [Reason:] MIPS R2000 possess RISC architecture in which the processor executes its instruction in a single clock cycle and also synthesize complex operations from the same reduced instruction set.

6. How is memory accessed in RISC architecture?
a) load and store instruction
b) opcode instruction
c) memory instruction
d) bus instruction

View Answer

Answer: a [Reason:] The data of memory address is loaded into a register and manipulated, its contents are written out to the main memory.

7. Which of the following has a Harvard architecture?
a) EDSAC
b) SSEM
c) PIC
d) CSIRAC

View Answer

Answer: c [Reason:] PIC follows Harvard architecture in which the external bus architecture consist of separate buses for instruction and data whereas SSEM, EDSAC, CSIRAC are stored program architecture.

8. Which of the following statements are true for von Neumann architecture?
a) shared bus between the program memory and data memory
b) separate bus between the program memory and data memory
c) external bus for program memory and data memory
d) external bus for data memory only

View Answer

Answer: a [Reason:] von Neumann architecture shares bus between program memory and data memory whereas Harvard architecture have a separate bus for program memory and data memory.

9. What is CAM stands for?
a) content-addressable memory
b) complex addressable memory
c) computing addressable memory
d) concurrently addressable memory

View Answer

Answer: a [Reason:] Non-von Neumann architecture is based on content-addressable memory.

10. Which of the following processors uses Harvard architecture?
a) TEXAS TMS320
b) 80386
c) 80286
d) 8086

View Answer

Answer: a [Reason:] It is a digital signal processor which have small and highly optimized audio or video processing signals. It possesses multiple parallel data bus.

11. Which company further developed the study of RISC architecture?
a) Intel
b) Motorola
c) university of Berkeley
d) MIPS

View Answer

Answer: c [Reason:] The University of Berkeley and Stanford university provides the basic architecture model of RISC.

12. Princeton architecture is also known as
a) von Neumann architecture
b) Harvard
c) RISC
d) CISC

View Answer

Answer: a [Reason:] The von Neumann architecture is also known as von Neumann model or Princeton architecture.

13. Who coined the term RISC?
a) David Patterson
b) von Neumann
c) Michael J Flynn
d) Harvard

View Answer

Answer: a [Reason:] David Patterson of Berkeley university coined the term RISC whereas Michael J Flynn who first views RISC.

14. Which of the following is an 8-bit RISC Harvard architecture?
a) AVR
b) Zilog80
c) 8051
d) Motorola 6800

View Answer

Answer: a [Reason:] AVR is an 8-bit RISC architecture developed by Atmel. Zilog80, 8051, Motorola 6800 are having CISC architectures.

15. Which of the following processors has CISC architecture?
a) AVR
b) Atmel
c) Blackfin
d) Zilog Z80

View Answer

Answer: d [Reason:] Zilog80 have CISC architecture whereas AVR, Atmel and blackfin possess RISC architecture.

Set 2

1. Which of the following can be used for long distance communication?
a) I2C
b) Parallel port
c) SPI
d) RS232

View Answer

Answer: d [Reason:] A slightly different serial port called RS232 is used for long distance communication, otherwise the clock may get skewed. The low voltage signal also affect the long distance communication.

2. Which of the following can affect the long distance communication?
a) clock
b) resistor
c) inductor
d) capacitor

View Answer

Answer: a [Reason:] For small distance communication, the clock signal which allows a synchronous transmission of data is more than enough, and the low voltage signal of TTL or CMOS is sufficient for the operation. But for long distance communication, the clock signal may get skewed and the low voltage can be affected by the cable capacitance. So for long distance communication RS232 can be used.

3. Which are the serial ports of the IBM PC?
a) COM1
b) COM4 and COM1
c) COM1 and COM2
d) COM3

View Answer

Answer: c [Reason:] The IBM PC has one or two serial ports called the COM1 and the COM2, which are used for the data transmission between the PC and many other peripheral units like printer, modem etc.

4. Which of the following can provide hardware handshaking?
a) RS232
b) Parallel port
c) Counter
d) Timer

View Answer

Answer: a [Reason:] In RS232, several lines are used for transmitting and receiving data and these also provide a control for the hardware handshaking.

5. Which of the following have an asynchronous data transmission?
a) SPI
b) RS232
c) Parallel port
d) I2C

View Answer

Answer: b [Reason:] The data is transmitted asynchronously in RS232 which enhance long distance communication, whereas SPI, I2C offers short distance communication, and therefore, they are using synchronous data transmission.

6. How many areas does the serial interface have?
a) 1
b) 3
c) 2
d) 4

View Answer

Answer: c [Reason:] The serial interface is divided into two, physical interface and the electrical interface.

7. The RS232 is also known as
a) UART
b) SPI
c) Physical interface
d) Electrical interface

View Answer

Answer: d [Reason:] The RS232 is also known as the physical interface and it is also known as EIA232.

8. How much voltage does the MC1489 can take ?
a) 12V
b) 5V
c) 3.3V
d) 2.2V

View Answer

Answer: b [Reason:] The MC1489 is a interface chip which can take a 5V and generate internally the other voltages which are needed to meet the interface specification.

9. Which of the following is not a serial protocol?
a) SPI
b) I2C
c) Serial port
d) RS232

View Answer

Answer: d [Reason:] The RS232 is a physical interface. It does not follow the serial protocol.

10. Which of the following is an ideal interface for LCD controllers?
a) SPI
b) parallel port
c) Serial port
d) M-Bus

View Answer

Answer: d [Reason:] M-Bus or Motorola Bus is an ideal interface for LCD controllers, A/D converters, EEPROMs and many other components which can benefit faster transmission.

Set 3

1. Which of the following are the pin efficient method of communicating between other devices?
a) serial port
b) parallel port
c) peripheral port
d) memory port

View Answer

Answer: a [Reason:] The serial ports are considered to be the pin efficient method of communication between other devices within an embedded system.

2. Which of the following depends the number of bits that are transferred?
a) wait statement
b) ready statement
c) time
d) counter

View Answer

Answer: c [Reason:] The time taken for the data transmission within the system depends on the clock frequency and the number of bits that are transferred.

3. Which of the following is the most commonly used buffer in the serial porting?
a) LIFO
b) FIFO
c) FILO
d) LILO

View Answer

Answer: b [Reason:] Most of the serial ports uses a FIFO buffer so that the data is not lost. The FIFO buffer is read to receive the data, that is, first in first out.

4. What does SPI stand for?
a) serial parallel interface
b) serial peripheral interface
c) sequential peripheral interface
d) sequential port interface

View Answer

Answer: b [Reason:] The serial parallel interface bus is a commonly used interface which involves master slave mechanism. The shift registers are worked as master and the slave devices are driven by a common clock.

5. Which allows the full duplex synchronous communication between the master and the slave?
a) SPI
b) serial port
c) I2C
d) parallel port

View Answer

Answer: a [Reason:] The serial peripheral interface allows the full duplex synchronous communication between the master and the slave devices. MC68HC05 developed by Motorola uses SPI for interfacing the peripheral devices.

6. Which of the following processor uses SPI for interfacing?
a) 8086
b) 8253
c) 8254
d) MC68HC11

View Answer

Answer: d [Reason:] The MC68HC05 and MC68HC11 microcontrollers uses the serial peripheral interface for the peripheral interfacing.

7. In which register does the data is written in the master device?
a) index register
b) accumulator
c) SPDR
d) status register

View Answer

Answer: c [Reason:] The serial peripheral interface follows a master slave mechanism in which the data is written to the SPDR register in the master device and clocked out into the slave device SPDR by using a common clock signal called SCK.

8. What happens when 8 bits are transferred in the SPI?
a) wait statement
b) ready statement
c) interrupt
d) remains unchanged

View Answer

Answer: c [Reason:] The interrupts are locally generated when 8-bits are transferred so that the data can be read before the next byte is clocked through.

9. Which signal is used to select the slave in the serial peripheral interfacing?
a) slave select
b) master select
c) interrupt
d) clock signal

View Answer

Answer: a [Reason:] The slave select signal selects which slave is to receive data from the master.

10. How much time period is necessary for the slave to receive the interrupt and transfer the data?
a) 4 clock time period
b) 8 clock time period
c) 16 clock time period
d) 24 clock time period

View Answer

Answer: b [Reason:] The SPI uses an eight clock time period for the slave to receive the interrupt and transfer the data which determines the maximum data rate.

Set 4

1. Which of the following cache has a separate comparator for each entry?
a) direct mapped cache
b) fully associative cache
c) 2-way associative cache
d) 16-way associative cache

View Answer

Answer: b [Reason:] A fully associative cache have a comparator for each entry so that all the entries can be tested simultaneously.

2. What is the disadvantage of a fully associative cache?
a) hardware
b) software
c) memory
d) peripherals

View Answer

Answer: a [Reason:] The major disadvantage of the fully associative cache is the amount of hardware needed for the comparison increases in proportion to the cache size and hence, limits the fully associative cache.

3. How many comparators present in the direct mapping cache?
a) 3
b) 2
c) 1
d) 4

View Answer

Answer: c [Reason:] The direct mapping cache have only one comparator so that only one location possibly have all the data irrespective of the cache size.

4. Which mapping of cache is inefficient in software viewpoint?
a) fully associative
b) 2 way associative
c) 16 way associative
d) direct mapping

View Answer

Answer: d [Reason:] The direct mapping cache organization is simple from the hardware design aspects but it is inefficient in the software viewpoint.

5. Which mechanism splits the external memory storage into memory pages?
a) index mechanism
b) burst mode
c) distributive mode
d) a software mechanism

View Answer

Answer: a [Reason:] The index mechanism splits the external memory storage into a series of memory pages in which each page is the same size of the cache. Each page is mapped to the cache so that each page can have its own location in the cache.

6. Which of the following cache mapping can prevent bus thrashing?
a) fully associative
b) direct mapping
c) n way set associative
d) 2 way associative

View Answer

Answer: c [Reason:] Only one data can be accessed in direct mapping that is, if one word is accessed at a time, all other words are discarded at the same time. This is known as bus thrashing which can be solved by splitting up the caches so there are 2,4,..n possible entries available. The major advantage of the set associative cache is its capability to prevent the bus thrashing at the expense of hardware.

7. Which cache mapping have a sequential execution?
a) direct mapping
b) fully associative
c) n way set associative
d) burst fill

View Answer

Answer: d [Reason:] The burst fill mode of cache mapping have a sequential nature of executing instructions and data access. The instruction fetches and execution accesses to sequential memory locations until it has a jump instruction or a branch instruction. This kind of cache mapping is seen in MC68030 processor.

8. Which address is used for a tag?
a) memory address
b) logical address
c) cache address
d) location address

View Answer

Answer: b [Reason:] The cache memory uses either a physical address or logical address for its tag data. For a logical cache, the tag refers to a logical address and for a physical cache, the tag refers to the physical address.

9. In which of the following the data is preserved within the cache?
a) logical cache
b) physical cache
c) unified cache
d) harvard cache

View Answer

Answer: b [Reason:] In the physical cache, the data is preserved within the cache because it does not flush out during the context switching but on the other hand, the logical cache flushes out the data and clear it during a context switching.

10. What is the disadvantage of the physical address?
a) debugging
b) delay
c) data preservation
d) data cleared

View Answer

Answer: b [Reason:] The physical address access the data through the memory management unit which causes a delay.

11. Which cache memory solve the cache coherency problem?
a) physical cache
b) logical cache
c) unified cache
d) harvard cache

View Answer

Answer: a [Reason:] The physical cache is more efficient and can provide the cache coherency problem solved and MMU delay are kept to a minimum. PowerPC is an example for this advantage.

12. What type of cache is used in the Intel 80486DX?
a) logical
b) physical
c) harvard
d) unified

View Answer

Answer: d [Reason:] The Intel 80486DX processor has a unified cache. Similarly, Motorola MPC601PC also uses the unified cache. The unified cache has the same mechanism to store both data and instructions.

13. Which of the following has a separate cache for the data and instructions?
a) unified
b) harvard
c) logical
d) physical

View Answer

Answer: b [Reason:] The Harvard cache have a separate cache for the data and the instruction whereas the unified cache has a same cache for the data and instructions.

14. Which type of cache is used the SPARC architecture?
a) unified
b) harvard
c) logical
d) physical

View Answer

Answer: c [Reason:] The SPARC architecture uses logical cache whereas most of the internal cache designed now, uses physical cache because data is not flushed out in this cache.

15. Which of the following approach uses more silicon area?
a) unified
b) harvard
c) logical
d) physical

View Answer

Answer: b [Reason:] The Harvard architecture have a separate bus for data and instruction, therefore, it requires more area. It also uses more silicon area for the second set of tags and the comparators.

Set 5

1. What does SPARC stand for?
a) scalable processor architecture
b) speculating architecture
c) speculating processor
d) scaling Pentium architecture

View Answer

Answer: a [Reason:] SPARC was designed for optimizing compilers and easily pipelined hardware implementations and it can license by anyone that is, having a nonproprietary architecture which is used to develop various microprocessors.

2. How many bits does SPARC have?
a) 8
b) 16
c) 32
d) 64

View Answer

Answer: c [Reason:] It is a 32 bit RISC architecture having 32-bit wide register bank.

3. Which company developed SPARC?
a) intel
b) IBM
c) Motorola
d) sun microsystem

View Answer

Answer: d [Reason:] SPARC is developed by Sun Microsystem but different manufacturers from other companies like Intel, Texas worked on it.

4. What improves the context switching and parameter passing?
a) register windowing
b) large register
c) stack register
d) program counter

View Answer

Answer: a [Reason:] SPARC follows Berkeley architecture model and uses register windowing in order to improve the context switching and parameter passing. It also supports superscalar operations.

5. How many external interrupts does SPARC processor support?
a) 5
b) 10
c) 15
d) 20

View Answer

Answer: c [Reason:] SPARC processor provides 15 external interrupts which are generated by the interrupt lines IRL0-IRL3.

6. Which level is an in-built nonmaskable interrupt in SPARC processor?
a) 15
b) 14
c) 13
d) 12

View Answer

Answer: a [Reason:] The level 15 of the SPARC processor is assigned to be a nonmaskable interrupt and the remaining 14 levels are unmasked and if necessary they can be made maskable.

7. How many instructions does SPARC processor have?
a) 16
b) 32
c) 64
d) 128

View Answer

Answer: c [Reason:] The instruction set of SPARC processor have 64 instructions which can be accessed by load and store operation with an RISC architecture.

8. What is generated by an external interrupt in SPARC?
a) internal trap
b) external trap
c) memory trap
d) interfaced trap

View Answer

Answer: a [Reason:] In SPARC when an external interrupt is generated, an internal trap is created in the trap base register in which the current and next instructions are saved, the pipeline gets flushed and the processor turns into a supervisor mode.

9. When an external interrupt is generated, what type of mode does the processor supports?
a) real mode
b) virtual mode
c) protected mode
d) supervisor mode

View Answer

Answer: d [Reason:] In SPARC when an external interrupt is called, it creates an internal trap in which the current and next instructions get saved and mode of the processor switches to supervisor mode.

10. Where is trap vector table located in SPARC processor?
a) program counter
b) Y register
c) status register
d) trap base register

View Answer

Answer: d [Reason:] The trap vector table is located in the trap base register which supplies the address of the service routine. When it is completed REIT instructions are executed.

11. How many bits does SPARC-V9 processor have?
a) 16
b) 32
c) 64
d) 128

View Answer

Answer: c [Reason:] There are three major versions of SPARC which are SPARC-V7, SPARC-V8 and SPARC-V9. The former two are 32 bits processor and the later is a 64-bit processor.

12. What are the three modules in SPARC processor?
a) IU, FPU, CU
b) SP, DI, SI
c) AX, BX, CX
d) CU, CH, CL

View Answer

Answer: a [Reason:] The SPARC processor has three modules which are Integer unit, Floating point unit, and coprocessor unit. Each module has its own functions and integer unit controls the overall operation of the processor.

13. How many floating point register does the FPU of the SPARC have?
a) 16 128-bit
b) 32 128-bit
c) 64 128-bit
d) 10 128-bit

View Answer

Answer: a [Reason:] It possesses 32 32-bit single precision, 32 64-bit double precision and 16 128-bit quads precise floating registers.

14. Which module of SPARC contains the general purpose registers?
a) IU
b) FPU
c) CU
d) control unit

View Answer

Answer: a [Reason:] Integer unit contains the general purpose registers and it controls the overall operation and performance of the processor and the memory address is also calculated by the integer unit.