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Multiple choice question for engineering

Set 1

1. Which of the following is the biggest challenge in the cache memory design?
a) delay
b) size
c) coherency
d) memory access

View Answer

Answer: c [Reason:] The coherency is a major challenge in designing the cache memory. The cache has to be designed by solving the problem of data coherency while remaining hardware and software compatible.

2. What arises when a copy of data is held both in the cache and in the main memory?
a) stall data
b) stale data
c) stop data
d) wait for the state

View Answer

Answer: b [Reason:] The stale data arises when the copy is held both in the cache memory and in the main memory. If either copy is modified, the other data become stale and the system coherency can be destroyed.

3. In which writing scheme does all the data writes go through to main memory and update the system and cache?
a) write-through
b) write-back
c) write buffering
d) no caching of writing cycle

View Answer

Answer: a [Reason:] There are different writing scheme in the cache memory which increases the cache efficiency and one such is the write-through in which all the data go to the main memory and can update the system as well as the cache.

4. In which writing scheme does the cache is updated but main memory is not updated?
a) write-through
b) write-back
c) no caching of writing cycle
d) write buffering

View Answer

Answer: b [Reason:] The cache write-back mechanism needs a bus snooping system for the coherency. In this write-back scheme, the cache is updated first and the main memory is not updated.

5. In which writing scheme does the cache is not updated?
a) write-through
b) write-back
c) write buffering
d) no caching of writing cycle

View Answer

Answer: d [Reason:] The no caching write cycle does not update the cache but the data is written to the cache. If the previous data had cached, that entry is invalid and will not use. This makes the processor fetch data directly from the main memory.

6. Which writing mechanism forms the backbone of the bus snooping mechanism?
a) write-back
b) write-through
c) no caching of write cycles
d) write buffer

View Answer

Answer: c [Reason:] The no caching of write cycle seems to be wasteful because it does not update the cache, and if any previous data is cached, that entry might be an error and is not used. So the processor access data from the main memory but this writing scheme forms the backbone of the bus snooping system for the coherency issue.

7. What is the main idea of the writing scheme in the cache memory?
a) debugging
b) accessing data
c) bus snooping
d) write-allocate

View Answer

Answer: c [Reason:] There are four main writing scheme in the cache memory which is, write-through, write-back, no caching of the write cycle and write buffer. All these writing schemes are designed for bus snooping which can reduce the coherency.

8. In which scheme does the data write via a buffer to the main memory?
a) write buffer
b) write-back
c) write-through
d) no caching of the write cycle

View Answer

Answer: a [Reason:] The write-buffer is slightly similar to the write-through mechanism in which data is written to the main memory but in write buffer mechanism data writes to the main memory via a buffer.

9. Which of the following can allocate entries in the cache for any data that is written out?
a) write-allocate cache
b) read-allocate cache
c) memory-allocate cache
d) write cache

View Answer

Answer: a [Reason:] A write-allocate cache allocates the entries in the cache for any data that is written out. If the data is transferred to the external memory so that, when it is accessed again, the data is already waiting in the cache. It works efficiently if the size of the cache is large and it does not overwrite even though it is advantageous.

10. Which of the following uses a bus snooping mechanism?
a) MC88100
b) 8086
c) 8051
d) 80286

View Answer

Answer: a [Reason:] The bus snooping mechanism uses a combination of cache tag status, write policies and bus monitoring to ensure coherency. MC88100 or MC88200 uses bus snooping mechanism.

11. What lead to the development of MESI and MEI protocol?
a) cache size
b) cache coherency
c) bus snooping
d) number of caches

View Answer

Answer: b [Reason:] The problem of cache coherency lead to the formation of two standard mechanisms called MESI and MEI protocol. MC88100 have MESI protocol and MC68040 uses an MEI protocol.

12. Which of the following is also known as Illinois protocol?
a) MESI protocol
b) MEI protocol
c) Bus snooping
d) Modified exclusive invalid

View Answer

Answer: a [Reason:] The MESI protocol is also known as Illinois protocol because of its formation at the University of Illinois.

13. What does MESI stand for?
a) modified exclusive stale invalid
b) modified exclusive shared invalid
c) modified exclusive system input
d) modifies embedded shared invalid

View Answer

Answer: b [Reason:] The MESI protocol supports a shared state which is a formal mechanism for controlling the cache coherency by using the bus snooping techniques. MESI refers to the states that cached data can access. In MESI protocol, multiple processors can cache shared data.

14. What does MEI stand for?
a) modified embedded invalid
b) modified embedded input
c) modified exclusive invalid
d) modified exclusive input

View Answer

Answer: c [Reason:] MEI protocol is less complex and is easy to implement. It does not allow shared state for the cache.

15. Which protocol does MPC601 use?
a) MESI protocol
b) MEI protocol
c) MOSI protocol
d) MESIF protocol

View Answer

Answer: a [Reason:] MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor specific. So different processors have different cache coherency implementations.

Set 2

1. Which is the first device which started microprocessor revolution by Intel?
a) 8080
b) 8086
c) 8087
d) 8088

View Answer

Answer: a [Reason:] 8086 was released in 1978 and 8088 was released in 1979 .8087 is a numeric coprocessor which was released in 1977. Furthermore, 8080 is a device designed by intel in 1974.

2. Which is the first microprocessor by Motorola?
a) MC6800
b) MC68001
c) MIPS
d) powerPC

View Answer

Answer: a [Reason:] MC6800 is the first microprocessor by Motorola which started a revolution to the embedded systems.

3. Motorola MC6800 is a how many it processor?
a) 4
b) 8
c) 16
d) 32

View Answer

Answer: b [Reason:] MC6800 is an 8-bit processor and having two 8 bit accumulator registers.

4. How many accumulator does an MC6800 have?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] MC6800 is having 2 accumulators both comprising of 8 bits.

5. How many bit does an accumulator of MC6800 have?
a) 8
b) 16
c) 32
d) 4

View Answer

Answer: a [Reason:] MC6800 possess 8-bit accumulator register since it is an 8-bit processor.

6. What is the performance of an accumulator?
a) Storing data and performing logical operation
b) Storing data and performing arithmetic operation
c) Storing address
d) Pointer

View Answer

Answer: b [Reason:] Accumulator is used for all the arithmetic operation such as addition, subtraction, multiplication, relational, logical etc. It is also used for storage.

7. Which of the following is the area of memory that is used for storage?
a) Register
b) Stack
c) Accumulator
d) Memory

View Answer

Answer: b [Reason:] Stack can be used at the time of function call or it is a short time large scale storage of data. Therefore, stack is the area within memory for storage.

8. How a stack is accessed?
a) Stack pointer
b) Stack address
c) Stack bus
d) Stack register

View Answer

Answer: a [Reason:] Stack pointer is a special register that indexes into the stack.

9. PUSH-POP mechanism is seen in
a) Stack pointer
b) Register
c) Memory
d) Index register

View Answer

Answer: a [Reason:] Stack pointer is used to store data like subroutine calls in which a push-pop mechanism is followed. Data is pushed into the stack to store it and popped off to retrieve it.

10. 8 bits equals
a) 128 bytes
b) 64 bytes
c) 256 bytes
d) 32 bytes

View Answer

Answer: c [Reason:] 28 = 256 by which bytes are calculated.

11. What is the address range in 80286?
a) 1 Mbytes
b) 2 Mbytes
c) 16 Mbytes
d) 32 mbytes

View Answer

Answer: c [Reason:] 80286 is a 16 bit processor. So it have an address range of 16 Mbytes.

12. Which is the first 32 bit member of Intel?
a) 8086
b) 8088
c) 80286
d) 80386

View Answer

Answer: d [Reason:] The new generation of Intel starts with 80386 which have 32 bit registers.

13 What supports multitasking in 80386?
a) Read mode
b) External paging memory management unit
c) Paging and segmentation
d) On-chip paging memory management unit

View Answer

Answer: d [Reason:] Because of the efficient paging mechanism of 80386 in the memory management unit it supports multitasking that is, different tasks can be done at a time, a kind of parallel porting.

Set 3

1. Which is the very basic technique of refreshing DRAM?
a) refresh cycle
b) burst refresh
c) distributive refresh
d) software refresh

View Answer

Answer: a [Reason:] The DRAM needs to be periodically refreshed and the very basic technique is a special refresh cycle, during these cycles no other access is permitted. The whole chip is refreshed within a particular time period otherwise, the data will be lost.

2. How is refresh rate calculated?
a) by refresh time
b) by the refresh cycle
c) by refresh cycle and refresh time
d) refresh frequency and refresh cycle

View Answer

Answer: c [Reason:] The time required for refreshing the whole chip is known as refresh time. The number of access needed to complete refresh is called as the number of cycles. The number of cycles divided by the refresh time gives the refresh rate.

3. Which is the commonly used refresh rate?
a) 125 microseconds
b) 120 microseconds
c) 130 microseconds
d) 135 microseconds

View Answer

Answer: a [Reason:] There are two refresh rates used in common. They are standard refresh rate of 15.6 microseconds and 125 microseconds which the extended form.

4. How can we calculate the length of the refresh cycle?
a) twice of normal access
b) thrice of normal access
c) five times of normal access
d) six times of normal access

View Answer

Answer: a [Reason:] Each of the refresh cycles is approximately as twice as the length of the normal access, for example, a 70ns DRAM has a refresh cycle time of 130ns.

5. What type of error occurs in the refresh cycle of the DRAM?
a) errors in data
b) power loss
c) timing issues
d) not accessing data

View Answer

Answer: c [Reason:] When the refresh cycle in a DRAM is running, it will not access data, so the processor will have to wait for its data. This arises some timing issues.

6. What is the worst case delay of the burst refresh in 4M by 1 DRAM?
a) 0.4ms
b) 0.2ms
c) 170ns
d) 180ns

View Answer

Answer: b [Reason:] A 4M by 1 DRAM have 1024 refresh cycles. Bursting delay will be 0.2ms that is, the worst case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns.

7. Which refresh techniques depends on the size of time critical code for calculating refresh cycle?
a) burst refresh
b) distributed refresh
c) refresh cycle
d) software refresh

View Answer

Answer: b [Reason:] Most of the system uses the distributed method and depending on the size of the time critical code, the number of refresh cycles can be calculated.

8. Which of the following uses a timer for refresh technique?
a) RAS
b) CBR
c) software refresh
d) CAS

View Answer

Answer: c [Reason:] The software refresh performs the action by using a routine to periodically cycle through the memory and refreshes. It uses a timer in the program generating an interrupt. This interrupt performs the refreshing part in the DRAM.

9. What is the main disadvantage in the software refresh of the DRAM?
a) timer
b) delay
c) programming delay
d) debugging

View Answer

Answer: d [Reason:] Debugging in software refresh is very difficult to perform because they may stop the refreshing and if the refreshing is stopped, the contents get lost.

10. Which refresh technique is useful for low power consumption?
a) Software refresh
b) CBR
c) RAS
d) Burst refresh

View Answer

Answer: b [Reason:] CBR that is, CAS before RAS refresh is the one which is commonly used. It has low power consumption quality because it does not have address bus and the buffers can be switched off. It is worked by using an internal address counter which is stored on the memory chip itself and this can be incremented periodically.

11. Which refreshing techniques generates a recycled address?
a) RAS
b) CBR
c) Distributed refresh
d) Software refresh

View Answer

Answer: a [Reason:] The row address is placed on the address bus and the column address is held off which generates the recycle address. The address generation is done by an external hardware controller.

12. Which of the following uses a software refresh in the DRAM/
a) 8086
b) 80386
c) Pentium
d) Apple II personal computer

View Answer

Answer: d [Reason:] The Apple II personal computer have a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.

13. How do CBR works?
a) by asserting CAS before RAS
b) by asserting CAS after RAS
c) by asserting RAS before CAS
d) by asserting CAS only

View Answer

Answer: a [Reason:] CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.

14. Which of the refresh circuit is similar to CBR?
a) software refresh
b) hidden refresh
c) burst refresh
d) distribute refresh

View Answer

Answer: b [Reason:] In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. In the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of RAS signal at the end of the read cycle starts a CBR refresh cycle.

15. Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle?
a) IEEE
b) RAPID
c) JEDEC
d) UNESCO

View Answer

Answer: c [Reason:] The maximum time interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification.

Set 4

1. Which can prevent the terminal of data transmission?
a) flow control
b) increasing flow
c) increasing count
d) terminal count

View Answer

Answer: a [Reason:] The flow control can prevent the data transmission. It can also prevent the computer from sending more data than the other can cope with.

2. Which of the following is the first flow control method?
a) software handshaking
b) hardware handshaking
c) UART
d) SPI

View Answer

Answer: b [Reason:] The first flow control method is the hardware handshaking in which the hardware in the UART detects the potential overrun and it will assert a handshake line to tell the other UART to stop the transmission.

3. Which one of the following is the second method for flow controlling?
a) hardware
b) peripheral
c) software
d) memory

View Answer

Answer: c [Reason:] In the first method of flow control, there is a chance of data loss. So the second method of the flow control is adopted in which it uses a software to send characters XON and XOFF. XOFF can stop the data transfer and XON can restart the data transfer.

4. Which can restart the data transmission?
a) XON
b) XOFF
c) XRST
d) restart button

View Answer

Answer: a [Reason:] The second method of flow control is called software which is based on certain characters called XON and XOFF. XOFF can stop the data transfer and XON can restart the data transfer.

5. Which of the following is a common connector?
a) UART
b) SPI
c) I2C
d) DB-25

View Answer

Answer: d [Reason:] There are two connectors which are used very commonly. They are DB-25 and DB-9 which has 25 pins and 9 pins respectively.

6. What does pin 22 in DB-25 indicates?
a) transmit data
b) receive data
c) ring indicator
d) signal ground

View Answer

Answer: c [Reason:] The 22nd pin in DB-25 and the 9th pin in the DB-9 indicates a ring indicator which is asserted when a connected modem has detected an incoming call.

7. Which pin indicates the DSR in DB-25?
a) 1
b) 2
c) 4
d) 6

View Answer

Answer: d [Reason:] The 6th pin in DB-25 indicates DSR, that is, data set ready which indicates that each side is powered on and is ready to access data.

8. Which of the following connections are one to one?
a) modem cables
b) SPI
c) UART
d) I2C

View Answer

Answer: a [Reason:] The modem cables are straight cables which allows one to one connections without crossover.

9. Which of the following are used to link PCs?
a) modem cable
b) null modem cable
c) serial port
d) parallel port

View Answer

Answer: b [Reason:] The modem cables are used to link PC with other peripherals like printers, plotters, modems etc. But it cannot link with other PCs. So an alternative method is adopted to link PCs which is called null modem cable.

10. Which of the following method is used by Apple Macintosh?
a) hardware handshaking
b) software handshaking
c) no handshaking
d) null modem cable

View Answer

Answer: b [Reason:] The Apple Macintosh and UNIX use software handshaking for the data transmission where the characters are sent to control the flow of characters between two systems.

Set 5

1. How many bit register set does RISC 1 model used?
a) 138*24
b) 138*32
c) 69*16
d) 69*32

View Answer

Answer: b [Reason:] RISC 1 model is developed in the 1970s and uses a large register set of 138*32 bit. These are arranged in eight overlapping windows which have 24 registers each and these windows are split so that six registers can be used during function calls.

2. Which of the following processor commercializes the Berkeley RISC model?
a) SPARC
b) Stanford
c) RISC-1
d) RISC

View Answer

Answer: a [Reason:] The Berkeley RISC design was developed between the year 1980 and 1984 and later on the RISC design were commercialized as SPARC processor.

3. How many transistors does RISC 1 possess?
a) 44000
b) 45000
c) 44500
d) 45500

View Answer

Answer: c [Reason:] The final design of RISC concept is called the RISC 1 which was published by ACM ISCA. It possesses 44500 transistors which can implement 31 instruction.

4. How many registers does RISC 1 model have?
a) 68
b) 58
c) 78
d) 88

View Answer

Answer: c [Reason:] The RISC 1 model have 78 registers of size 32 bits.

5. Which of the architectures are made to speed up the processor?
a) CISC
b) RISC
c) program stored
d) von Neumann

View Answer

Answer: b [Reason:] RISC architecture is made for speeding up the processor with limited execution time whereas CISC architecture is mainly for code efficiency.

6. How did 8086 pass its control to 8087?
a) BUSY instruction
b) ESCAPE instruction
c) CONTROL instruction
d) fetch 8087

View Answer

Answer: b [Reason:] When 8086 comes across any floating point arithmetic operations, it executes ESCAPE instruction code in order to pass the control of bus and instruction op-code to 8087.

7. Which of the following processor supports MMX instructions?
a) 8080
b) 80486
c) Intel Pentium
d) 80386

View Answer

Answer: c [Reason:] MMX instructions or multimedia extensions were introduced in Pentium processors to provide support for multimedia software running on a PC.

8. Which of the following processors has a speculative execution?
a) 80486
b) P1
c) Intel Pentium
d) Pentium pro

View Answer

Answer: d [Reason:] Speculative execution is executed speculatively that is, following the predicted branch paths in the code until the true path is determined. If the processor executes correctly, then the performance is gained, if not, the results are discarded and the processor continues to execute until the correct path is identified.

9. How many bit accumulator does DSP56000 have?
a) 28
b) 56
c) 112
d) 14

View Answer

Answer: b [Reason:] The ALU of DSP56000 have two 56-bit accumulator A and B each of which have small register with it.

10. How many additional registers does DSP56000 have?
a) 2
b) 4
c) 6
d) 8

View Answer

Answer: b [Reason:] In addition to the six registers of DSP56000, it has four 24-bit registers X1,X0,Y1,Y0 which can be concatenated to form 48 bit register X and Y.

11. What does MAC instruction of DSP56000 stand for?
a) multiply accumulator
b) multiple access
c) multiple accounting
d) multiply accumulator counter

View Answer

Answer: a [Reason:] When MAC instruction is executed, the two of the 24-bit additional registers are multiplied together and then added or subtracted from A and B. It takes place in a single machine cycle of 75ns at 27MHz.