1. RTN stands for _____
a) Register Transfer Notation
b) Register Transmission Notation
c) Regular Transmission Notation
d) Regular Transfer Notation
Answer
Answer:a [Reason:]
2. The instruction, Add Loc,R1 in RTN is _______
a) AddSetCC Loc+R1
b) R1=Loc+R1
c) Not possible to write in RTN
d) R1<-[Loc]+[R1].
Answer
Answer:d [Reason:]
3. Can you perform addition on three operands simultaneously in ALN using Add instruction ?
a) Yes
b) Not possible using Add, we’ve to use AddSetCC
c) Not permitted
d) None of the mentioned
Answer
Answer:c [Reason:]
4. The instruction, Add R1,R2,R3 in RTN is _______
a) R3=R1+R2+R3
b) R3<-[R1]+[R2]+[R3].
c) R3=[R1]+[R2].
d) R3<-[R1]+[R2].
Answer
Answer:d [Reason:]
5. In a system, which has 32 registers the register id is ____ long.
a) 16 bit
b) 8 bits
c) 5 bits
d) 6 bits
Answer
Answer:c [Reason:]
6. The two phases of executing an instruction are ____
a) Instruction decoding and storage
b) Instruction fetch and instruction execution
c) Instruction execution and storage
d) Instruction fetch and Instruction processing
Answer
Answer:b [Reason:]
7. The Instruction fetch phase ends with ___
a) Placing the data from the address in MAR into MDR
b) Placing the address of the data into MAR
c) Completing the execution of the data and placing its storage address into MAR
d) Decoding the data in MDR and placing it in IR
Answer
Answer:d [Reason:]
8. While using the iterative construct (Branching) in execution ____ instruction is used to check the condition.
a) TestAndSet
b) Branch
c) TestCondn
d) None of the mentioned
Answer
Answer:b [Reason:]
9. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which is called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
Answer
Answer:a [Reason:]
10. The condition flag Z is set to 1 to indicate _______
a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
Answer
Answer:c [Reason:]