Computer Networks MCQ Number 01548

Computer Networks MCQ Set 1

1. The return address of the Sub-routine is pointed to by _______
a) IR
b) PC
c) MAR
d) Special memory registers

Answer

Answer: b [Reason:] The return address from the sub routine is pointed to by the PC.

2. The location to return to, from the subroutine is stored in _______
a) TLB
b) PC
c) MAR
d) Link registers

Answer

Answer: d [Reason:] The registers store the return address of the routine and is pointed to by the PC.

3. Subroutine nesting means,
a) Having multiple subroutines in a program
b) Using a linking nest statement to put many sub routines under the same name
c) Having one routine call the other
d) None of the mentioned

Answer

Answer: c [Reason:] None.

4. The order in which the return addresses are generated and used is _________
a) LIFO
b) FIFO
c) Random
d) Highest priority

Answer

Answer: a [Reason:] That is the routine called first is returned first.

5. In case of nested subroutines the return addresses are stored in __________
a) System heap
b) Special memory buffers
c) Processor stack
d) Registers

Answer

Answer: c [Reason:] In this case, there will be more number of return addresses it is stored on the processor stack.

6. The appropriate return addresses is obtained by the help of ____ in case of nested routines.
a) MAR
b) MDR
c) Buffers
d) Stack-pointers

Answer

Answer: d [Reason:] The pointers are used to point to the location on the stack where the address is stored.

7. When, parameters are being passed on to the subroutines they are stored in ________
a) Registers
b) Memory locations
c) Processor stacks
d) All of the mentioned

Answer

Answer: d [Reason:] In case of, parameter passing the data can be stored on any of the storage space.

8. The most efficient way of handling parameter passing is by using ______
a) General purpose registers
b) Stacks
c) Memory locations
d) None of the mentioned

Answer

Answer: a [Reason:] By using general purpose registers for the parameter passing we make the process more efficient.

9. The most Flexible way of logging the return addresses of the sub routines is by using _______
a) Registers
b) Stacks
c) Memory locations
d) None of the mentioned

Answer

Answer: b [Reason:] The stacks are used as Logs for return addresses of the sub routines.

10. The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i) The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user
a) i,ii and iv
b) ii and iii
c) iv
d) iii and iv

Answer

Answer: d [Reason:] None.

Computer Networks MCQ Set 2

1. The throughput of a super scalar processor is
a) less than 1
b) 1
c) More than 1
d) Not Known

Answer

Answer: c [Reason:] The throughput of a processor is measured by using the number of instructions executed per second.

2. When the processor executes multiple instructions at a time it is said to use _______
a) single issue
b) Multiplicity
c) Visualization
d) Multiple issue

Answer

Answer: d [Reason:] None.

3. The ______ plays a very vital role in case of super scalar processors.
a) Compilers
b) Motherboard
c) Memory
d) Peripherals

Answer

Answer: a [Reason:] The compilers are programmed to arrange the instructions to get more throughput.

4. If an exception is raised and the succeeding instructions are executed completly, then the processor is said to have ______
a) Exception handling
b) Imprecise exceptions
c) Error correction
d) None of the mentioned

Answer

Answer: b [Reason:] The processor since as executed the following instructions even though an exception was raised, hence the exception is treated as imprecise.

5. In super-scalar mode, all the similar instructions are grouped and executed together.
a) True
b) False

Answer

Answer: a [Reason:] The instructions are grouped meaning that the instructions fetch and decode and other cycles are overlapped.

6. In super-scalar processors, ________ mode of execution is used.
a) In-order
b) Post order
c) Out of order
d) None of the mentioned

Answer

Answer: c [Reason:] It follows out of order execution to speed up the execution of instructions.

7. Since it uses the out of order mode of execution, the results are stored in ______
a) Buffers
b) Special memory locations
c) Temporary registers
d) TLB

Answer

Answer: c [Reason:] The results are stored in temporary locations and are arranged afterwards.

8. The step where in the results stored in the temporary register is transfered into the permanent register is called as ______
a) Final step
b) Committment step
c) Last step
d) Inception step

Answer

Answer: b [Reason:] None.

9. A special unit used govern the out of order execution of the instructions is called as ______
a) Commitment unit
b) Temporal unit
c) Monitor
d) Supervisory unit

Answer

Answer: a [Reason:] This unit monitors the the execution of the instructions and makes sure that the final result is in order.

10. The commitment unit uses a queue called ______
a) Record buffer
b) Commitment buffer
c) Storage buffer
d) None of the mentioned

Answer

Answer: a [Reason:] None.

Computer Networks MCQ Set 3

1. The primary function of the BUS is
a) To connect the various devices to the cpu
b) To provide a path for communication between the processor and other devices
c) To facilitate data transfer between various devices
d) All of the mentioned

Answer

Answer: a [Reason:] The BUS is used to allow the passage of commands and data between cpu and devices.

2. The classification of BUSes into synchronous and asynchronous is based on
a) The devices connected to them
b) The type of data transfer
c) The Timing of data transfers
d) None of the mentioned

Answer

Answer: c [Reason:] The BUS are classified into different types for convenience of use and depending on the device.

3. The device which starts data transfer is called
a) Master
b) Transactor
c) Distributor
d) Initiator

Answer

Answer: d [Reason:] The device which starts the data transfer is called as initiator.

4. The device which interacts with the initiator is
a) Slave
b) Master
c) Responder
d) Friend

Answer

Answer: a [Reason:] The device which recieves the commands from the initiator for data transfer.

5. In synchronous BUS, the devices get the timing signals from
a) Timing generator in the device
b) A common clock line
c) Timing signals are not used at all
d) None of the mentioned

Answer

Answer: b [Reason:] The devices recieve their timing signals from the clock line of the BUS.

6. The delays caused in the switching of the timing signals is due to
a) Memory access time
b) WMFC
c) Propogation delay
d) Processor delay

Answer

Answer: c [Reason:] The time taken for the signal to reach the BUS from the device or the circuit accounts for this delay.

7. The time for which the data is to be on the BUS is affected by
a) Propagation delay of the circuit
b) Setup time of the device
c) Memory access time
d) Propagation delay of the circuit & Setup time of the device

Answer

Answer: d [Reason:] The time for which the data is held is larger than the time taken for propogation delay and setup time.

8. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
a) True
b) False

Answer

Answer: a [Reason:] None.

9. Which is fed into the BUS first by the initiator..??
a) Data
b) Address
c) Commands or controls
d) Address, Commands or controls

Answer

Answer: d [Reason:] None.

10. _____________ signal is used as an acknowledgement signal by the slave in Multiple cycle transfers.
a) Ack signal
b) Slave ready signal
c) Master ready signal
d) Slave recieval signal

Answer

Answer: b [Reason:] The slave once it recieves the commands and address from the master strobes the ready line indicating to the master that the commands are recieved.

Computer Networks MCQ Set 4

1. The difference between DRAM’s and SDRAM’s is/are ________
a) The DRAM’s will not use the master slave relationship in data transfer
b) The SDRAM’s make use of clock
c) The SDRAM’s are more power efficient
d) None of the mentioned

Answer

Answer: d [Reason:] The SDRAM’s make use of clock signals to synchronise their operation.

2. The difference in address and data connection between DRAM’s and SDRAM’s is
a) The usage of more number of pins in SDRAM’s
b) The requirement of more address lines in SDRAM’s
c) The usage of buffer in SDRAM’s
d) None of the mentioned

Answer

Answer: c [Reason:] The SDRAM uses buffered storage of address and data.

3. A _______ is used to restore the contents of the cells.
a) Sense amplifier
b) Refresh counter
c) Restorer
d) None of the mentioned

Answer

Answer: b [Reason:] The Counter helps to restore the charge on the capacitor.

4. The mode register is used to
a) Select the row or column data transfer mode
b) Select the mode of operation
c) Select mode of storing the data
d) All of the mentioned

Answer

Answer: b [Reason:] The mode register is used to choose between burst mode or bit mode of operation.

5. In a SDRAM each row is refreshed every 64ms.
a) True
b) False

Answer

Answer: a [Reason:] None.

6. The time taken to transfer a word of data to or from the memory is called as ______
a) Access time
b) Cycle time
c) Memory latency
d) None of the mentioned

Answer

Answer: c [Reason:] The performance of the memory is measured by means of latency.

7. In SDRAM’s buffers are used to store data that is read or written.
a) True
b) False

Answer

Answer: a [Reason:] In SDRAm’s all the bytes of data to be read or written are stored in the buffer until the operation is complete.

8. The SDRAM performs operation on the _______
a) Rising edge of the clock
b) Falling edge of the clock
c) Middle state of the clock
d) Transition state of the clock

Answer

Answer: a [Reason:] The SDRAM’s are edge-triggered.

9. DDR SDRAM’s perform fster data transfer by
a) Integrating the hardware
b) Transfering on both edges
c) Improving the clock speeds
d) Increasing the bandwidth

Answer

Answer: b [Reason:] By transfering data on both the edges the bandwidth is effectively doubled.

10. To improve the data retrieval rate
a) The memory is divided into two banks
b) The hardware is changed
c) The clock frequency is increased
d) None of the mentioned

Answer

Answer: a [Reason:] The division of memory into two banks makes it easy to access two different words at each edge of the clock.

Computer Networks MCQ Set 5

1. The transfer rate, when the USB is operating in low-speed of operation is _____
a) 5 Mb/s
b) 12 Mb/s
c) 2.5 Mb/s
d) 1.5 Mb/s

Answer

Answer: d [Reason:] The USB has two rates of operation the low-speed and the full-speed one.

2. THe high speed mode of operation of the USB was introduced by _____
a) ISA
b) USB 3.0
c) USB 2.0
d) ANSI

Answer

Answer: c [Reason:] The high-speed mode of operation was introduced with USB 2.0,which enabled the USB to operatte at 480 Mb/s.

3. The sampling process in speaker output is a ________ process.
a) Asynchronous
b) Synchronous
c) Isochronous
d) None of the mentioned

Answer

Answer: c [Reason:] The isochronous process means each bit of data is seperated by a time interval.

4. The USB device follows _______ structure.
a) List
b) Huffmann
c) Hash
d) Tree

Answer

Answer: d [Reason:] The USB has a tree structure with the root hub at the centre.

5. The I/O devices form the _____ of the tree structure.
a) Leaves
b) Subordinate roots
c) Left sub trees
d) Right sub trees

Answer

Answer: a [Reason:] The I/o devices form the leaves of the structure.

6. USB is a parallel mode of transmission of data and this enables for the fast speeds of data transfers.
a) True
b) False

Answer

Answer: b [Reason:] The USB does a serial mode of data transfer.

7. In USB the devices can communicate with each other.
a) True
b) False

Answer

Answer: b [Reason:] It allows only the host to communicate with the devices and not between themselves.

8. The device can send a message to the host by taking part in _____ for the communication path.
a) Arbitration
b) Polling
c) Prioritising
d) None of the mentioned

Answer

Answer: b [Reason:] None.

9. When the USB is connected to a system, its root hub is connected to the ________
a) PCI BUS
b) SCSI BUS
c) Processor BUS
d) IDE

Answer

Answer: c [Reason:] The USB’s root is connected to the processor directly using the BUS.

10. The devices connected to USB is assigned an ____ adrress.
a) 9 bit
b) 16 bit
c) 4 bit
d) 7 bit

Answer

Answer: d [Reason:] To make it easier for recognition the devices are given 7 bit addresses.

11. The USB address space can be shared by the user’s memory space.
a) True
b) False

Answer

Answer: b [Reason:] The USB memory space is not under any address sapces and cannot be accessed.

12. The initial address of a device just connected to the HUB is ____ .
a) AHFG890
b) 0000000
c) FFFFFFF
d) 0101010

Answer

Answer: b [Reason:] By standard the usual address of a new device is zero.

13. Locations in the device to or from which data transfers can take place is called ____
a) End points
b) Hosts
c) Source
d) None of the mentioned

Answer

Answer: a [Reason:] None.

14. A USB pipe is a ______ channel.
a) Simplex
b) Half-Duplex
c) Full-Duplex
d) Both Simplex and Full-Duplex

Answer

Answer: c [Reason:] This means that the pipe is bi-directional in sending messages or information.

15. The type/s of packets sent by the USB is/are _______
a) Data
b) Address
c) Control
d) Both Data and Control

Answer

Answer: d [Reason:] This means that the usb gets both data and control signlas required for the transfer operation.