Computer Networks MCQ Number 01547

Computer Networks MCQ Set 1

1. The main reason for the discontinuation of semi conductor based storage devices for providing large storage space is _________
a) Lack of sufficient resources
b) High cost per bit value
c) Lack of speed of operation
d) None of the mentioned

Answer

Answer: b [Reason:] In case of semi conductor based memory technology, we get speed but the increase in the integration of various devices the cost is high.

2. The digital information is stored on the hard disk by ____________
a) Applying a suitable electric pulse
b) Applying a suitable magnetic field
c) Applying a suitable nuclear field
d) By using optic waves

Answer

Answer: a [Reason:] The digital data is sorted on the magnetized discs by magnetizing the areas.

3. For the synchronization of the read head, we make use of a _______
a) Framing bit
b) Synchronization bit
c) Clock
d) Dirty bit

Answer

Answer: c [Reason:] The clock makes it easy to distinguish between different values red by head.

4. On of the most widely used schemes of encoding used is _________
a) NRZ-polar
b) RZ-polar
c) Manchester
d) Block encoding

Answer

Answer: c [Reason:] The Manchester encoding used is also called as phase encoding and it is used to encode both clock and data.

5. The drawback of Manchester encoding is _________
a) The cost of the encoding scheme
b) The speed of encoding the data
c) The Latency offered
d) The low bit storage density provided

Answer

Answer: d [Reason:] The space required to represent each bit must be large enough to accommodate two changes in magnetization.

6. The read/write heads must be near to disk surfaces for better storage.
a) True
b) False

Answer

Answer: a [Reason:] By maintaining the heads near to the surface greater bit densities can be achieved.

7. _____ pushes the heads away from the surface as they rotate at their standard rates.
a) Magnetic tension
b) Electric force
c) Air pressure
d) None of the mentioned

Answer

Answer: c [Reason:] Due to the speed of rotation of the discs air pressure develops in the hard disk.

8. The air pressure can be countered by putting ______ in the head-disc surface arrangement.
a) Air filter
b) Spring mechanism
c) coolant
d) None of the mentioned

Answer

Answer: b [Reason:] The spring mechanism pushes the head along the surface to reduce the air pressure effect.

9. The method of placing the heads and the discs in an air tight environment is called as ______
a) RAID Arrays
b) ATP tech
c) Winchester technology
d) Fleming reduction

Answer

Answer: c [Reason:] The Disks and the heads operate faster due to the absence of the dust particles.

10. A hard disk with 20 surfaces will have _____ heads.
a) 10
b) 5
c) 1
d) 20

Answer

Answer: d [Reason:] Each surface will have its own head to perform read/write operation.

Computer Networks MCQ Set 2

1. The mode of transmission of data, where one bit is sent for each clock cycle is ______
a) Asynchronous
b) Parallel
c) Serial
d) Isochronous

Answer

Answer: d [Reason:] In isochronous mode of transmission, each bit of the data is sent per each cycle.

2. The transformation between the Parallel and serial ports is done with the help of ______
a) Flip flops
b) Logic circuits
c) Shift registers
d) None of the mentioned

Answer

Answer: c [Reason:] The Shift registers are used to output the data in a desired format based on the need.

3. The serial port is used to connect basically _____ and processor.
a) I/O devices
b) Speakers
c) Printer
d) Monitor

Answer

Answer: a [Reason:] The serial port is used to connect keyboard and other devices which input or output one bit at a time.

4. The double buffer is used for
a) Enabling receival of multiple bits of input
b) Combining the input and output operations
c) Extending the buffer capacity
d) None of the mentioned

Answer

Answer: a [Reason:] None.

5. ______ to increase the flexibility of the serial ports.
a) The wires used for ports is changed
b) The ports are made to allow different clock signals for input and output
c) The drivers are modified
d) All of the mentioned

Answer

Answer: b [Reason:] The ports are made more flexible by enabling the input or output of different clock signals for different devices.

6. UART stands for ________
a) Universal Asynchronous Relay Transmission
b) Universal Accumulator Register Transfer
c) Universal Asynchronous Receiver Transmitter
d) None of the mentioned

Answer

Answer: c [Reason:] The UART is a standard developed for designing serial ports.

7. The key feature of UART is
a) Its architectural design
b) Its simple implementation
c) Its general purpose usage
d) Its enhancement of connecting low speed devices

Answer

Answer: d [Reason:] None.

8. The data transfer in UART is done in ______
a) Asynchronous start stop format
b) Synchrnous start stop format
c) Isochronous format
d) EBDIC format

Answer

Answer: a [Reason:] This basically means that the data transfer is done in asynchronous mode.

9. The standard used in serial ports to facilitate communication is _____
a) RS-246
b) RS-LNK
c) RS-232-C
d) Both RS-246 and RS-LNK

Answer

Answer: c [Reason:] This is a standard which acts as a protocol for message communication involving serial ports.

10. In serial port interface, the INTR line is connected to _____
a) Status register
b) Shift register
c) Chip select
d) None of the mentioned

Answer

Answer: a [Reason:] None.

Computer Networks MCQ Set 3

1. The CPU is also called as ________
a) Processor hub
b) ISP
c) Controller
d) All of the mentioned

Answer

Answer: b [Reason:] ISP stands for Instruction Set Processor.

2. A common strategy for performance is making various functional units operate parallely.
a) True
b) False

Answer

Answer: a [Reason:] By parallely accessing data we can have a pipelined processor.

3. The PC gets incremented
a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
d) None of the mentioned

Answer

Answer: c [Reason:] The PC always points to the next instruction to be executed.

4. Which register in the processor is single directional ?
a) MAR
b) MDR
c) PC
d) Temp

Answer

Answer: a [Reason:] The MAR is single directional as it just takes the address from the processor bus and passes it to the external bus.

5. The transparent register/s is/are __________
a) Y
b) Z
c) Temp
d) All of the mentioned

Answer

Answer: d [Reason:] These registers are usually used to store temporary values.

6. Which register is connected to the MUX ?
a) Y
b) Z
c) R0
d) Temp

Answer

Answer: a [Reason:] The MUX can either read the operand from the Y register or increment the PC.

7. The registers,ALU and the interconnecting path together are called as ______
a) Control path
b) Flow path
c) Data path
d) None of the mentioned

Answer

Answer: c [Reason:] None.

8. The input and output of the registers are governed by __________
a) Transistors
b) Diodes
c) Gates
d) Switches

Answer

Answer: d [Reason:] None.

9. When two or more clock cycles are used to complete data transfer it is called as ________
a) Single phase clocking
b) Multi-phase clocking
c) Edge triggered clocking
d) None of the mentioned

Answer

Answer: b [Reason:] This is basically used in systems without edge-triggered flip flops.

10. ________ signal is used to show complete of memory operation.
a) MFC
b) WMFC
c) CFC
d) None of the mentioned

Answer

Answer: a [Reason:] MFC stands for Memory Function Complete.

Computer Networks MCQ Set 4

1. ______ is used as an intermediate to extend the processor BUS.
a) Bridge
b) Router
c) Connector
d) Gateway

Answer

Answer: a [Reason:] The bridge circuit is basically used to extend the processor BUS to connect devices.

2. ________ is an extension of the processor BUS.
a) SCSI BUS
b) USB
c) PCI BUS
d) None of the mentioned

Answer

Answer: c [Reason:] The PCI BUS is used as an extension of the processor BUS and devices connected to it, is like connected to the Processor itself.

3. ISA stands for
a) International American Standard
b) Industry Standard Architecture
c) International Standard Architecture
d) None of the mentioned

Answer

Answer: b [Reason:] The ISA is a architectural standard developed by IBM for its PC’s.

4. ANSI stands for
a) American National Standards Institute
b) Architectural National Standards Institute
c) Asian National Standards Institute
d) None of the mentioned

Answer

Answer: a [Reason:] The ANSI is one of the standard architecture used by companies in designing the systems.

5. The video devices are connected to ______ BUS.
a) PCI
b) USB
c) HDMI
d) SCSI

Answer

Answer: d [Reason:] The SCSI BUS is used to connect the video devices to processor by providing a parallel BUS.

6. SCSI stands for ___________
a) Signal Computer System Interface
b) Small Computer System Interface
c) Small Coding System Interface
d) Signal Coding System Interface

Answer

Answer: b [Reason:] The SCSI BUS is used to connect disks and video controllers.

7. ISO stands for __________
a) International Standards Organisation
b) International Software Organisation
c) Industrial Standards organisation
d) Industrial Software Organisation

Answer

Answer: a [Reason:] The ISO is yet another architectural standard, used to design systems.

8. The system developed by IBM with ISA architecture is ______
a) SPARC
b) SUN-SPARC
c) PC-AT
d) None of the mentioned

Answer

Answer: c [Reason:] None.

9. IDE disk is connected to the PCI BUS using ______ interface.
a) ISA
b) ISO
c) ANSI
d) IEEE

Answer

Answer: a [Reason:] None.

10. IDE stands for _________
a) Intergrated Device Electronics
b) International Device Encoding
c) Industrial Decoder Electronics
d) International Decoder Encoder

Answer

Answer: a [Reason:] The IDE interface is used to connect the harddisk to the processor in most of the Pentium processors.

Computer Networks MCQ Set 5

1. The duration between the read and the mfc signal is ______
a) Access time
b) Latency
c) Delay
d) Cycle time

Answer

Answer: a [Reason:] The time between the issue of read signal and the completion of it is called memory access time.

2. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
d) None of the mentioned

Answer

Answer: a [Reason:] The Time taken by the cpu to end one read operation and to start one more is cycle time.

3. MFC is used to _________
a) Issue a read signal
b) Signal to the device that the memory read operation is complete
c) Signal the processor the memory operation is complete
d) Assign a device to perform the read operation

Answer

Answer: c [Reason:] The MFC stands for memory Function Complete.

4. __________ is the bootleneck, when it comes computer performance.
a) Memory access time
b) Memory cycle time
c) Delay
d) Latency

Answer

Answer: b [Reason:] The processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance.

5. The logical addresses generated by the cpu are mapped onto physical memory by ____
a) Relocation register
b) TLB
c) MMU
d) None of the mentioned

Answer

Answer: c [Reason:] The MMU stands for memory management unit, which is used to map logical address onto phsical address.

6. VLSI stands for ___________
a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
d) None of the mentioned

Answer

Answer: a [Reason:] None.

7. The cells in a row are connected to a common line called ______
a) Work line
b) Word line
c) Length line
d) Principle diagonal

Answer

Answer: b [Reason:] This means that the cell contents together form one word of instruction or data.

8. The cells in each column are connected to ______
a) Word line
b) Data line
c) Read line
d) Sense/ Write line

Answer

Answer: d [Reason:] The cells in each column are connected to the sense/write circuit using two bit lines and which is inturn connected to the data lines.

9. The word line is driven by the _____
a) Chip select
b) Address decoder
c) Data line
d) Control line

Answer

Answer: b [Reason:] None.

10. A 16 X 8 organisation of memory cells, can store upto _____
a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits

Answer

Answer: d [Reason:] It can store upto 128 bits as each cell can hold one bit of data.

11. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised into _____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1

Answer

Answer: d [Reason:] All the others require less than 10 address bits.

12. Circuits that can hold their state as long as power is applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache

Answer

Answer: b [Reason:] None.

13. The number of external connections required in 16 X 8 memory organisation is _____
a) 14
b) 19
c) 15
d) 12

Answer

Answer: a [Reason:] In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.

14. The advantage of CMOS SRAM over the transistor one’s is _________
a) Low cost
b) High efficiency
c) High durability
d) Low power consumption

Answer

Answer: d [Reason:] This is because the cell consumes power only when it is being accessed.

15. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
a) 10
b) 8
c) 9
d) 12

Answer

Answer: c [Reason:] To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation).