Computer Networks MCQ Set 1
1. The memory blocks are mapped on to the cache with the help of ______
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the mentioned
Answer
Answer: c [Reason:]
2. During a write operation if the required block is not present in the cache then ______ occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
Answer
Answer: d [Reason:]
3. In ________ protocol the information is directly written into main memory.
a) Write through
b) Write back
c) Write first
d) None of the mentioned
Answer
Answer: a [Reason:]
4. The only draw back of using the early start protocol is _______
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
Answer
Answer: b [Reason:]
5. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______
a) Set associative
b) Associative
c) Direct
d) Indirect
Answer
Answer: c [Reason:]
6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used for ________
a) Tag
b) Block
c) Word
d) Id
Answer
Answer: a [Reason:]
7. In direct mapping the presence of the block in memory is checked with the help of block field.
a) True
b) False
Answer
Answer: b [Reason:]
8. In associative mapping, in a 16 bit system the tag field has ______ bits.
a) 12
b) 8
c) 9
d) 10
Answer
Answer: a [Reason:]
9. The associative mapping is costlier than direct mapping.
a) True
b) False
Answer
Answer: a [Reason:]
10. The technique of searching for a block by going through all the tags is ______
a) Linear search
b) Binary search
c) Associative search
d) None of the mentioned
Answer
Answer: c [Reason:]
11. The set associative map technique is a combination of the direct and associative technique.
a) True
b) False
Answer
Answer: a [Reason:]
12. In set-associative technique, the blocks are grouped into ______ sets.
a) 4
b) 8
c) 12
d) 6
Answer
Answer: d [Reason:]
13. A control bit called ____ has to be provided to each blocj in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
d) All of the mentioned
Answer
Answer: b [Reason:]
14. The bit used to indicate whether the block was recently used or not is _______
a) Idol bit
b) Control bit
c) Refernece bit
d) Dirty bit
Answer
Answer: d [Reason:]
15. Data which is not up-to date is called as _______
a) Spoilt data
b) Stale data
c) Dirty data
d) None of the mentioned
Answer
Answer: b [Reason:]
Computer Networks MCQ Set 2
1. The smallest entity of memory is called as _______
a) Cell
b) Block
c) Instance
d) Unit
Answer
Answer: a [Reason:]
2. The collection of the above mentioned entities where data is stored is called as ______
a) Block
B) Set
c) Word
d) Byte
Answer
Answer: c [Reason:]
3. An 24 bit address generates an address space of ______ locations.
a) 1024
b) 4096
c) 2 48
d) 16,777,216
Answer
Answer: d [Reason:]
4. If a system is 64 bit machine , then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
Answer
Answer: b [Reason:]
5. The type of memory assignment used in Intel processors is _____
a) Little Endian
b) Big Endian
c) Medium Endian
d) None of the mentioned
Answer
Answer: a [Reason:]
6. When using the Big Endian assignment to store a number, the sign bit of the number is stored in _____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the mentioned
Answer
Answer: a [Reason:]
7. To get the physical address from the logical address generated by CPU we use ____
a) MAR
b) MMU
c) Overlays
d) TLB
Answer
Answer: b [Reason:]
8. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
Answer
Answer: c [Reason:]
9. During transfer of data between the processor and memory we use ______
a) Cache
b) TLB
C) Buffers
d) Registers
Answer
Answer: d [Reason:]
10. Physical memory is divided into sets of finite size called as ______
a) Frames
b) Pages
c) Blocks
d) Vectors
Answer
Answer: a [Reason:]
Computer Networks MCQ Set 3
1. Add #%01011101,R1 , when this instruction is executed then _________
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place , whereas this is similar to a MOV instruction
d) None of the mentioned
Answer
Answer: a [Reason:]
2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use ___ symbol before the operand.
a) ~
b) !
c) $
d) *
Answer
Answer: c [Reason:]
3. When generating physical addresses from logical address the offset is stored in _____
a) Translation look-aside buffer
b) Relocation register
c) Page table
d) Shift register
Answer
Answer: b [Reason:]
4. The technique used to store programs larger than the memory is ______
a) Overlays
b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
Answer
Answer: a [Reason:]
5. The unit which acts as an intermediate agent between memory and backing store to reduce process time is _____
a) TLB’s
b) Registers
c) Page tables
d) Cache
Answer
Answer: d [Reason:]
6. The Load instruction does the following operation/s,
a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) None of the mentioned
Answer
Answer: b [Reason:]
7. Complete the following analogy :- Registers are to RAM’s as Cache’s are to _____
a) System stacks
b) Overlays
c) Page Table
d) TLB
Answer
Answer: d [Reason:]
8. The BOOT sector files of the system are stored in _____
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Answer
Answer: b [Reason:]
9. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the mentioned
Answer
Answer: a [Reason:]
10. Which of the following technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both Dynamic linking and loading
Answer
Answer: c [Reason:]
Computer Networks MCQ Set 4
1. _____ register is designated to point to the 68000 processor stack.
a) A7 register
b) B2 register
c) There is no such designation
d) Any general purpose register is selected at random
Answer
Answer: a [Reason:]
2. The word length in the 68000 computer is _______
a) 32 bit
b) 64 bit
c) 16 bit
d) 8 bit
Answer
Answer: c [Reason:]
3. Is 68000 computer Byte addressable ?
a) True
b) False
Answer
Answer: a [Reason:]
4. The register in 68000 can contain up to _____ bits.
a) 24
b) 32
c) 16
d) 64
Answer
Answer: b [Reason:]
5. The 68000 has a max of how many data registers?
a) 16
b) 20
c) 10
d) 8
Answer
Answer: d [Reason:]
6. When an operand is stored in a register it is _______
a) Stored in the lower order bits of the register
b) Stored in the higher order bits of the register
c) Stored in any of the bits at random
d) None of the mentioned
Answer
Answer: a [Reason:]
7. The status register of the 68000 has ____ condition codes.
a) 7
b) 4
c) 5
d) 8
Answer
Answer: c [Reason:]
8. The 68000 uses _____ address assignment.
a) Big Endian
b) Little Endian
c) X-Little Endian
d) X-Big Endian
Answer
Answer: a [Reason:]
9. The addresses generated by the 68000 is _____ bit.
a) 32
b) 16
c) 24
d) 42
Answer
Answer: c [Reason:]
10. Instructions which can handle any type of addressing mode are said to be _____
a) Omniscious
b) Orthogonal
c) Versatile
d) None of the mentioned
Answer
Answer: b [Reason:]
Computer Networks MCQ Set 5
1. The general purpose registers are combined into a block called as ______
a) Register bank
b) Register Case
c) Register file
d) None of the mentioned
Answer
Answer: c [Reason:]
2. In ______ technology, the implementation of the register file is by using an array of memory locations.
a) VLSI
b) ANSI
c) ISA
d) ASCI
Answer
Answer: a [Reason:]
3. In a three BUS architecture, how many input and output ports are there ?
a) 2 output and 2 input
b) 1 output and 2 input
c) 2 output and 1 input
d) 1 output and 1 input
Answer
Answer: c [Reason:]
4. For a 3 BUS architecture, is the below code correct for adding three numbers ?
PCout, R = B, MARin , READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End
a) True
b) False
Answer
Answer: a [Reason:]
5. The main advantage of multiple bus organisation over single bus is __________
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
Answer
Answer: a [Reason:]
6. CISC stands for _________
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
Answer
Answer: c [Reason:]
7. If the instruction Add R1,R2,R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).
a) 3
b) ~2
C) ~1
d) 6
Answer
Answer: c [Reason:]
8. In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.
a) MUX
b) DE-MUX
c) En-CDS
d) None of the mentioned
Answer
Answer: a [Reason:]
9. There exists a seperate block consisting of various units to decode an instruction.
a) True
b) False
Answer
Answer: a [Reason:]
10. There exists a seperate block to increment the PC in multiple BUS organisation.
a) True
b) False
Answer
Answer: a [Reason:]