Computer Networks MCQ Number 01543

Computer Networks MCQ Set 1

1. ________ are the different type/s of generating control signals.
a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired

Answer

Answer: d [Reason:] The above are used to generate control signals in different types of system architectures.

2. The type of control signal are generated based on,
a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
d) All of the mentioned

Answer

Answer: d [Reason:] Based on the information above the type of control signal is decided.

3. What does the hardwired control generator consist of ?
a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned

Answer

Answer: d [Reason:] The CU uses the above blocks and IR to produce the necessary signal.

4. What does the end instruction do ?
a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor

Answer

Answer: c [Reason:] It is basically used to start the generation of a new signal.

5. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4 .BR…
a) True
b) False

Answer

Answer: a [Reason:] The signal is generated using the logic of the formula above.

6. What does the RUN signal do ?
a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one

Answer

Answer: d [Reason:] The RUN signal increments the step counter by one for each clock cycle.

7. The name hardwired came because the sequence of operations carried out are determined by the wiring.
a) True
b) False

Answer

Answer: a [Reason:] In other words hardwired is another name for Hardware Control signal generator.

8. The benefit of using this approach is
a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation

Answer

Answer: d [Reason:] None.

9. The disadvantage/s of the hardwired approach is
a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions

Answer

Answer: d [Reason:] The more complex the instruction set less applicable is hardwired approach.

10. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False

Answer

Answer: a [Reason:] None.

Computer Networks MCQ Set 2

1. The standard SRAM chips are costly as _________
a) They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
d) None of the mentioned

Answer

Answer: b [Reason:] As they require a large number of transistors, their cost per bit increases.

2. The drawback of building a large memory with DRAM is ______________
a) The large cost factor
b) The inefficient memory organisation
c) The Slow speed of operation
d) All of the mentioned

Answer

Answer: c [Reason:] The DRAM’s were used for large memory modules for a long time until a substitute was found.

3. To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.
a) True
b) False

Answer

Answer: a [Reason:] To improve the speed we use flash drives at the cost of memory space.

4. The fastest data access is provided using _______
a) Caches
b) DRAM’s
c) SRAM’s
d) Registers

Answer

Answer: d [Reason:] The fastest data access is provided using registers as these memory locations are situated inside the processor.

5. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB

Answer

Answer: a [Reason:] These memory devices are generally used to map onto the data stored in the larger memories.

6. The larger memory placed between the primary cache and the memory is called ______
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB

Answer

Answer: b [Reason:] This is basically used to provide effective memory mapping.

7. The next level of memory hierarchy after the L2 cache is _______
a) Secondary storage
b) TLB
c) Main memory
d) Register

Answer

Answer: d [Reason:] None.

8. The last on the hierarchy scale of memory devices is ______
a) Main memory
b) Secondary memory
c) TLB
d) Flash drives

Answer

Answer: b [Reason:] The secondary memory is the slowest memory device.

9. In the memory hierarchy, as the speed of operation increases the memory size also increases.
a) True
b) False

Answer

Answer: b [Reason:] As the speed of operation increases the cost increases and the size decreases.

10. If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy.
a) True
b) False

Answer

Answer: b [Reason:] The flash drives will increase the speed of transfer but still it wont be faster than primary memory.

Computer Networks MCQ Set 3

1. The address space of the IA-32 is ____
a) 2¹⁶
b) 2³²
c) 2⁶⁴
d) 2⁸

Answer

Answer: b [Reason:] The number of addressable locations in the memory is called as address space.

2. The addressing method used in IA-32 is ______
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little and Big Endian

Answer

Answer: a [Reason:] The method of addressing the data in the system.

3. The floating point numbers are stored in general purpose register in IA-32.
a) True
b) False

Answer

Answer: b [Reason:] The floating registers are not stored in general purpose registers as they have a real part and a decimal part.

4. The The Floating point registers of IA-32 can operate on operands up to _____
a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit

Answer

Answer: d [Reason:] The size of the floating numbers that can be stored in the floating register.

5. The size of the floating registers can be extended upto _____
a) 128 bit
b) 256 bit
c) 80 bit
d) 64 bit

Answer

Answer: c [Reason:] None.

6. The IA-32 architecture associates different parts of memory called ____ with different usages.
a) Frames
b) Pages
c) Tables
d) Segments

Answer

Answer: d [Reason:] The memory is divided into parts called as segments.

7. The PC is incorporated with the help of general purpose registers.
a) True
b) False

Answer

Answer: b [Reason:] Registers are not used to incorporate PC as in other architectures , but a separate space is allocated to it.

8. IOPL stands for ________
a) Input/Output Privilege level
b) Input Output Process Link
c) Internal Output Process Link
d) Internal Offset Privilege Level

Answer

Answer: a [Reason:] This indicates the security between the transfers between the I/O devices and memory.

9. In IA-32 architecture along with the general flags, the other conditional flags provided are _____
a) IOPL
b) IF
c) TF
d) All of the mentioned

Answer

Answer: d [Reason:] These flags are basically used check the system for exceptions.

10. The register used to serve as PC is called as _______
a) Indirection register
b) Instruction pointer
c) R-32
d) None of the mentioned

Answer

Answer: b [Reason:] The PC is used to store the next instruction that is going to be executed.

11. The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit .
a) True
b) False

Answer

Answer: a [Reason:] This switching enables a wide range of operations to be performed.

12. The Bit extension of the register is denoted with the help of ____ symbol.
a) $
b) `
c) E
d) ~

Answer

Answer: c [Reason:] This is used to extend the size of the register.

13. The instruction, ADD R1, R2, R3 is decoded as _______
a) R1<-[R1]+[R2]+[R3].
b) R3<-[R1]+[R2].
c) R3<-[R1]+[R2]+[R3].
d) R1<-[R2]+[R3].

Answer

Answer: d [Reason:] None.

14. The instruction JG loop , does
a) jumps to the memory location loop if the result of the most recent arithmetic op is even
b) jumps to the memory location loop if the result of the most recent arithmetic op is greater than 0
c) jumps to the memory location loop if the test condition is satisfied with the value of loop
d) none of the mentioned

Answer

Answer: b [Reason:] This instruction is used to cause a branch based the outcome of the arithmetic operation.

15. The LEA mnemonic is used to __________
a) Load the effective address of an instruction
b) Load the values of operands onto a accumulator
c) declare the values as global constants
d) Store the outcome of the operation at a memory location

Answer

Answer: a [Reason:] The effective address is the address of the memory location required for the execution of the instruction.

Computer Networks MCQ Set 4

1. The interrupt-request line is a part of the
a) Data line
b) Control line
c) Address line
d) None of the mentioned

Answer

Answer: b [Reason:] The Interrupt-request line is a control line along which the device is allowed to send the interrupt signal.

2. The return address from the interrupt-service routine is stored on the
a) System heap
b) Processor register
c) Processor stack
d) Memory

Answer

Answer: c [Reason:] The Processor after servicing the interrupts as to load the address of the previous process and this address is stored in the stack.

3. The signal sent to the device from the processor to the device after recieving an interrupt is
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal

Answer

Answer: a [Reason:] The Processor upon recieving the interrupt should let the device know that its request is received.

4. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i,iv
b) ii,iii and iv
c) iii,iv
d) i,ii

Answer

Answer: d [Reason:] None.

5. The time between the recieval of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time

Answer

Answer: b [Reason:] The delay in servicing of an interrupt happens due to the time taken for contect switch to take place.

6. Interrupts form an important part of _____ systems.
a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user

Answer

Answer: c [Reason:] This forms an imporatant part of the Real time system since if a process arrives with greater priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced.

7. A single Interrupt line can be used to service n different devices?
a) True
b) False

Answer

Answer: a [Reason:] None

8. ______ type circuits are generally used for interrupt service lines
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i,ii
b) ii
c) ii,iii
d) ii,iv

Answer

Answer: a [Reason:] None

9. The resistor which is attached to the service line is called _____
a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor

Answer

Answer: b [Reason:] This resistor is used to pull up the voltage of the interrupt service line.

10. An interrupt that can be temporarily ignored is
a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt

Answer

Answer: c [Reason:] The maskable interrupts are usually low priority interrupts which can be ignored if an higher priority process is being executed.

11. The 8085 microprocessor respond to the presence of an interrupt
a) As soon as the trap pin becomes ‘LOW’
b) By checking the trap pin for ‘high’ status at the end of each instruction fetch
c) By checking the trap pin for ‘high’ status at the end of execution of each instruction
d) By checking the trap pin for ‘high’ status at regular intervals

Answer

Answer: c [Reason:] The 8085 microprocessor are designed to complete the execution of the current instruction and then to service the interrupts.

12. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged
a) A hardware interrupt is needed
b) A software interrupt is needed
c) Either hardware or software interrupt is needed
d) A non-privileged instruction (which does not generate an interrupt)is needed

Answer

Answer: b [Reason:] A software interrupt by some program which needs some cPU service, at that time the two modes can be interchanged.

13. Which interrupt is unmaskable?
a) RST 5.5
b) RST 7.5
c) TRAP
d) Both RST 5.5 and 7.5

Answer

Answer: c [Reason:] The trap is a non-maskable interrupt as it deals with the on going process in the processor. THe trap is initiated by the process being executed due to lack of data required for its completion.Hence trap is unmaskable.

14. From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i,ii and iv
d) iv

Answer

Answer: d [Reason:] None.

15. How can the processor ignore other interrupts when it is servicing one
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the mentioned

Answer

Answer: d [Reason:] None.

Computer Networks MCQ Set 5

1. The chip can be disabled or cut off from external connection using ______
a) Chip select
b) LOCK
c) ACPT
d) RESET

Answer

Answer: a [Reason:] The chip gets enabled if the CS is set otherwise the chip gets disabled.

2. To organise large memory chips we make use of ______
a) Integrated chips
b) Upgraded hardware
c) Memory modules
d) None of the mentioned

Answer

Answer: c [Reason:] The cell blocks are arranged and put in a memory module.

3. The less space consideration as lead to the development of ________ (for large memories).
a) SIMM’s
b) DIMS’s
c) SSRAM’s
d) Both SIMM’s and DIMS’s

Answer

Answer: d [Reason:] The SIMM (single inline memory module) or DIMM (dual inline memory module) occupy less space while providing greater memory space.

4. The SRAM’s are basically used as ______
a) Registers
b) Caches
c) TLB
d) Buffer

Answer

Answer: b [Reason:] The SRAM’s are used as caches as their opeartion speed is very high.

5. The higher order bits of the address are used to _____
a) Specify the row address
b) Specify the column address
c) Input the CS
d) None of the mentioned

Answer

Answer: a [Reason:] None.

6. The address lines multiplexing is done using ______
a) MMU
b) Memory controller unit
c) Page table
d) Overlay geberator

Answer

Answer: b [Reason:] This unit multiplexes the various address lines to lesser pins on the chip.

7. The controller multiplexes the addresses after getting the _____ signal.
a) INTR
b) ACK
c) RESET
d) Request

Answer

Answer: d [Reason:] The controller gets the request from the device needing the memory read or write operation and then it multiplexes the address.

8. The RAS and CAS signals are provided by the ______
a) Mode register
b) CS
c) Memory controller
d) None of the mentioned

Answer

Answer: c [Reason:] The multiplexed signal of the controller is split into RAS and CAS.

9. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read opeartion. Then the refresh overhead of the chip is ______
a) 0.0021
b) 0.0038
c) 0.0064
d) 0.0128

Answer

Answer: b [Reason:] The refresh overhead is calculated by taking into account the total time for refreshing and the interval of each refresh.

10. When DRAM’s are used to build a complex large memory,then the controller only provides the refresh counter.
a) True
b) False

Answer

Answer: a [Reason:] None.