Computer Networks MCQ Number 01542

Computer Networks MCQ Set 1

1. The CISC stands for ___________
a) Computer Instruction Set Compliment
b) Complete Instruction Set Compliment
c) Computer Indexed Set Components
d) Complex Instruction set computer

Answer

Answer: d [Reason:] CISC is an computer architecture where in the processor performs more complex operations in one step.

2. The computer architecture aimed at reducing the time of execution of instructions is ________
a) CISC
b) RISC
c) ISA
d) ANNA

Answer

Answer: b [Reason:] The RISC stands for Reduced Instruction Set Computer.

3. The Sun micro systems processors usually follow _____ architecture.
a) CISC
b) ISA
c) ULTRA SPARC
d) RISC

Answer

Answer: d [Reason:] The Risc machine aims at reducing the instruction set of the computer.

4. The RISC processor has a more complicated design than CISC.
a) True
b) False

Answer

Answer: b [Reason:] The RISC processor design is more simpler than CISC and it consists of fewer transistors.

5. The iconic feature of the RISC machine among the following are
a) Reduced number of addressing modes
b) Increased memory size
c) Having a branch delay slot
d) All of the mentioned

Answer

Answer: c [Reason:] A branch delay slot is an instruction space immediately following a jump or branch.

6. Both the CISC and RISC architectures have been developed to reduce the ______
a) Cost
b) Time delay
c) Semantic gap
d) All of the mentioned

Answer

Answer: c [Reason:] The semantic gap is the gap between the high level language and the low level language.

7. Out of the following which is not a CISC machine.
a) IBM 370/168
b) VAX 11/780
c) Intel 80486
d) Motorola A567

Answer

Answer: d [Reason:] None.

8. Pipe-lining is a unique feature of _______
a) RISC
b) CISC
c) ISA
d) IANA

Answer

Answer: a [Reason:] The RISC machine architecture was the first to implement pipe-lining.

9. In CISC architecture most of the complex instructions are stored in _____
a) Register
b) Diodes
c) CMOS
d) Transistors

Answer

Answer: d [Reason:] In CISC architecture more emphasis is given on the instruction set and the instructions take over a cycle to complete.

10. Which of the architecture is power efficient?
a) CISC
b) RISC
c) ISA
d) IANA

Answer

Answer: b [Reason:] Hence the RISC architecture is followed in the design of mobile devices.

Computer Networks MCQ Set 2

1. The set of loosely connected computers are called as _____
a) LAN
b) WAN
c) Workstation
d) Cluster

Answer

Answer: d [Reason:] In a computer cluster all the participating computers work together on a particular task.

2. The each computer in a cluster is connected using _____
a) UTP
b) Rj-45
c) STP
d) Coaxial cable

Answer

Answer: b [Reason:] The computers are connected to each other using a LAN connector cable.

3. The computer cluster architecture emerged as a result of ____
a) ISA
b) Workstation
c) Super computers
d) Distributed systems

Answer

Answer: d [Reason:] A distributed system is a computer system spread out over a geographic area.

4. The software which governs the group of computers is _____
a) Driver Rd45
b) Interfacor UI
c) Clustering middleware
d) Distributor

Answer

Answer: c [Reason:] The software helps to project a single system image to the user.

5. The simplest form of a cluster is ______ approach.
a) Beowolf
b) Sequioa
c) Stone
d) None of the mentioned

Answer

Answer: a [Reason:] None.

6. The cluster formation in which the work is divided equally among the systems is ______
a) Load-configuration
b) Load-Division
c) Light head
d) Both Load-configuration and Load-Division

Answer

Answer: a [Reason:] This approach the work gets divided among the systems equally.

7. In the client server model of the cluster _____ approach is used.
a) Load configuration
b) FIFO
c) Bankers algorithm
d) Round robin

Answer

Answer: d [Reason:] By using this approach the performance of the cluster can be enhanced.

8. The beowolf structure follows the _____ approach of relationship between the systems.
a) Master-slave
b) Asynchronous
c) Synchronous
d) Isochronous

Answer

Answer: a [Reason:] None.

9. The most common modes of communication in clusters is/are ______
a) Message queues
b) Message passing interface
c) PVm
d) Both Message passing interface and PVm

Answer

Answer: d [Reason:] None.

10. The method followed in case of node failure, wherein the node gets disabled is _____
a) STONITH
b) Fibre channel
c) Fencing
d) None of the mentioned

Answer

Answer: a [Reason:] None.

Computer Networks MCQ Set 3

1. The DMA differs from the interrupt mode by
a) The involvement of the processor for the operation
b) The method accessing the I/O devices
c) The amount of data transfer possible
d) None of the mentioned

Answer

Answer: d [Reason:] DMA is an approcah of performing data transfers in bulk between memory and the external device without the intervention of the processor.

2. The DMA transfers are performed by a control circuit called as
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker

Answer

Answer: b [Reason:] The Controller performs the functions that would normally be carried out by the processor.

3. In DMA transfers, the required signals and addresses are given by the
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself

Answer

Answer: c [Reason:] The DMA controller acts like a processor for DMA transfers and overlooks the entire process.

4. After the complition of the DMA transfer the processor is notified by
a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the mentioned

Answer

Answer: b [Reason:] The controller raises an interrupt signal to notify the processor that the transfer was complete.

5. The DMA controller has _______ registers
a) 4
b) 2
c) 3
d) 1

Answer

Answer: c [Reason:] The Controller uses the registers to store the starting address,word count and the status of the operation.

6. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned

Answer

Answer: a [Reason:] None.

7. The controller is connected to the ____
a) Processor BUS
b) System BUS
c) External BUS
d) None of the mentioned

Answer

Answer: b [Reason:] The controller is directly connected to the system BUS to provide faster transfer of data.

8. Can a single DMA controller perform operations on two different disks simulteneously?
a) True
b) False

Answer

Answer: a [Reason:] The DMA controller can perform operations on two different disks if the appropriate details are known.

9. The techinique whereby the DMA controller steals the access cycles of the processor to operate is called
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing

Answer

Answer: c [Reason:] The controller takes over the processor’s access cycles and performs memory operations.

10. The technique where the controller is given complete access to main memory is
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode

Answer

Answer: d [Reason:] The controller is given full control of the memory access cycles and can transfer blocks at a faster rate.

11. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal echancers
c) Bridge circuits
d) All of the mentioned

Answer

Answer: a [Reason:] The controller stores the data to transfered in the buffer and then transfers it.

12. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned

Answer

Answer: b [Reason:] The BUS arbitrator is used overcome the contention over the BUS possession.

13. The registers of the controller are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits

Answer

Answer: c [Reason:] None.

14. When process requests for a DMA transfer
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed

Answer

Answer: d [Reason:] The process requesting the transfer is paused and the operation is performed , meanwhile another process is run on the processor.

15. The DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS

Answer

Answer: c [Reason:] The transfer can only be initiated by instruction of a program being executed.

Computer Networks MCQ Set 4

1. If during the execution of an instruction an exception is raised then
a) The instruction is executed and the exception is handled
b) The instruction is halted and the exception is handled
c) The processor completes the execution and saves the data and then handle the exception
d) None of the mentioned

Answer

Answer: b [Reason:] Since the interrupt was raised during the exevution of the instruction, the instruction cannot be executed and the exception is servied immediately.

2. _____ is/are types of exceptions.
a) Trap
b) Interrupt
c) System calls
d) All of the mentioned

Answer

Answer: d [Reason:] None.

3. The program used to find out errors is called
a) Debugger
b) Compiler
c) Assembler
d) Scanner

Answer

Answer: a [Reason:] Debugger is a program used to detect and correct errors in the program.

4. The two facilities provided by the debugger is
a) Trace points
b) Break points
c) Compile
d) Both Trace and Break points

Answer

Answer: d [Reason:] The debugger provides us with the two facilities to improve the checking of errors.

5. In trace mode of operation is ________
a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without rectification of errors
d) The program is alted only at specific points

Answer

Answer: a [Reason:] In trace mode the program is checked line by line and if errors are detected then exceptions are raised right away.

6. In Breakpoint mode of operation
a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without rectification of errors
d) The program is alted only at specific points

Answer

Answer: d [Reason:] The Breakpoint mode of operation allows the program to be alted at only specific locations.

7. The different modes of operation of a computer is
a) User and System mode
b) User and Supervisor mode
c) Supervisor and Trace mode
d) Supervisor, User and Trace mode

Answer

Answer: b [Reason:] The user programs are in the user mode and the system crucial programs are in the supervisor mode.

8. The instructions which can be run only supervisor mode are
a) Non-privileged instructions
b) System instructions
c) Privileged instructions
d) Exception instructions

Answer

Answer: c [Reason:] These instructions are those which can are crucial for the systems performance and hence cannot be adultered by user programs, so is run only in supervisor mode.

9. A privilege exception is raised
a) When a process tries to change the mode of the system
b) When a process tries to change the piority level of the other processes
c) When a process tries to access the memory allocated to other user
d) All of the mentioned

Answer

Answer: d [Reason:] None.

10. How is a privilege exception dealt with?
a) The program is alted and the system switches into supervisor mode and restarts the program execution
b) The Program is stopped and removed from the queue
c) The system switches the mode and starts the execution of a new process
d) The system switches mode and runs the debugger

Answer

Answer: a [Reason:] None.

Computer Networks MCQ Set 5

1. The logic operations are simpler to implement using logic circuits.
a) True
b) False

Answer

Answer: a [Reason:] The logic operation include AND, OR, XOR etc.

2. The logic operations are implemented using _______ circuits.
a) Bridge
b) Logical
c) Combinatorial
d) Gate

Answer

Answer: c [Reason:] The combinatorial circuits means, using the basic universal gates.

3. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________
a) Half adders
b) Full adders
c) Ripple adders
d) Fast adders

Answer

Answer: b [Reason:] In this the carry for the next step is generated in the previous steps operation.

4. The carry in the ripple adders(which is true)
a) Are generated at the beginning only
b) Must travel through the configuration
c) Is generated at the end of each operation
d) None of the mentioned

Answer

Answer: b [Reason:] The carry must pass through the configuration of the circuit till it reaches the particular step.

5. In full adders the sum circuit is implemented using ________
a) And & or gates
b) NAND gate
c) XOR
d) XNOR

Answer

Answer: c [Reason:] sum = a ^ b ^ c (‘^’ indicates XOR operation).

6. The usual implementation of the carry circuit involves _________
a) And and or gates
b) XOR
c) NAND
d) XNOR

Answer

Answer: b [Reason:] In case of full and half adders this method is used.

7. A _______ gate is used to detect the occurrence of an overflow.
a) NAND
b) XOR
c) XNOR
d) AND

Answer

Answer: b [Reason:] The overflow is detected by cn^cn-1 (‘^’ indicates XOR operation).

8. In a normal adder circuit the delay obtained in generation of the output is _______
a) 2n + 2
b) 2n
c) n + 2
d) None of the mentioned

Answer

Answer: a [Reason:] The 2n delay cause of the carry generation and the 2 delay cause of the XOR operation.

9. The final addition sum of the numbers, 0110 & 0110 is
a) 1101
b) 1111
c) 1001
d) 1010

Answer

Answer: a [Reason:] None.

10. The delay reduced to in the carry look ahead adder is _______
a) 5
b) 8
c) 10
d) 2n

Answer

Answer: a [Reason:] None.