Computer Networks MCQ Set 1
1. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
Answer
Answer: a [Reason:]
2. The instruction -> Add LOCA, R0 does _______
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
Answer
Answer: c [Reason:]
3. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
Answer
Answer: a [Reason:]
4. During the execution of a program which gets initialized first ?
a) MDR
b) IR
c) PC
d) MAR
Answer
Answer: c [Reason:]
5. Which of the register/s of the processor is/are connected to Memory Bus ?
a) PC
b) MAR
c) IR
d) Both PC and MAR
Answer
Answer: b [Reason:]
6. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer
Answer: a [Reason:]
7. The internal Components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer
Answer: b [Reason:]
8. ______ is used to choose between incrementing the PC or performing ALU operations.
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
Answer
Answer: b [Reason:]
9. The registers,ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
Answer
Answer: d [Reason:]
10. _______ is used to store data in registers.
a) D flip flop
b) JK flip flop
c) RS flip flop
d) None of the mentioned
Answer
Answer: a [Reason:]
Computer Networks MCQ Set 2
1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned
Answer
Answer: b [Reason:]
2. The device which is allowed to initiate data transfers on the BUS at any time is called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
Answer
Answer: a [Reason:]
3. ______ BUS arbitration appproach uses the involvement of the processor
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned
Answer
Answer: a [Reason:]
4. The circuit used for the request line is a _________
a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit
Answer
Answer: c [Reason:]
5. The Centralised BUS arbitration is similar to ______ interrupt circuit
a) Priority
b) Parallel
c) Single
d) Daisy chain
Answer
Answer: d [Reason:]
6. When the processor recieves the request from a device, it responds by sending _____
a) Acknowledge signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
Answer
Answer: b [Reason:]
7. In Centralised Arbitration ______ is/are is the BUS master
a) Processor
b) DMA controller
c) Device
d) Both Processor and DMA controller
Answer
Answer: d [Reason:]
8. Once the BUS is granted to a device ___________
a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned
Answer
Answer: a [Reason:]
9. The BUS busy line is made of ________
a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
Answer
Answer: b [Reason:]
10. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Processor
c) Controller
d) None of the mentioned
Answer
Answer: b [Reason:]
11. The BUS busy line is used
a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indiacate the BUS is already allocated
d) None of the mentioned
Answer
Answer: c [Reason:]
12. Distributed arbitration makes use of ______
a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID
Answer
Answer: d [Reason:]
13. In Distributed arbitration, the device requesting the BUS ______
a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
d) None of the mentioned
Answer
Answer: a [Reason:]
14. How is a device selected in Distributed arbitration ?
a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the mentioned
Answer
Answer: c [Reason:]
15. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration
a) Device A
b) Device B
c) Insufficient information
d) None of the mentioned
Answer
Answer: b [Reason:]
Computer Networks MCQ Set 3
1. The main virtue for using single Bus structure is ____________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of the mentioned
Answer
Answer: c [Reason:]
2. ______ are used to over come the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
Answer
Answer: d [Reason:]
3. To extend the connectivity of the processor bus we use ________
a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
Answer
Answer: a [Reason:]
4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
d) None of the mentioned
Answer
Answer: c [Reason:]
5. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
Answer
Answer: b [Reason:]
6. ANSI stands for __________
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
Answer
Answer: a [Reason:]
7. _____ register Connected to the Processor bus is a single-way transfer capable.
a) PC
b) IR
c) Temp
d) Z
Answer
Answer: d [Reason:]
8. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
Answer
Answer: b [Reason:]
9. The main advantage of multiple bus organisation over single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
Answer
Answer: a [Reason:]
10. The ISA standard Buses are used to connect ___________
a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
Answer
Answer: c [Reason:]
Computer Networks MCQ Set 4
1. The main memory is structured into modules each with its own address register called ______
a) ABR
b) TLB
c) PC
d) IR
Answer
Answer: a [Reason:]
2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
Answer
Answer: a [Reason:]
3. In memory interleaving, the lower order bits of the address is used to
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned
Answer
Answer: b [Reason:]
4. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
Answer
Answer: a [Reason:]
5. The number failed attempts to access memory, stated in the form of fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Answer
Answer: b [Reason:]
6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer
Answer: b [Reason:]
7. In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
Answer
Answer: a [Reason:]
8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
Answer
Answer: b [Reason:]
9. The extra time needed to bring the data into memory in case of a miss is called as _____
a) Delay
b) Propagation time
c) Miss penalty
d) None of the mentioned
Answer
Answer: c [Reason:]
10. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
a) True
b) False
Answer
Answer: a [Reason:]
Computer Networks MCQ Set 5
1. The reason for the implementation of the cache memory is ________
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
d) All of the mentioned
Answer
Answer: b [Reason:]
2. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
b) Memory localisation
c) Memory size
d) None of the mentioned
Answer
Answer: a [Reason:]
3. The temporal aspect of the locality of reference means
a) That the recently executed instruction wont be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
d) None of the mentioned
Answer
Answer: c [Reason:]
4. The spatial aspect of the locality of reference means
a) That the recently executed instruction is executed again next
b) That the recently executed wont be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed in future
Answer
Answer: d [Reason:]
5. The correspondence between the main memory blocks and those in the cache is given by _________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
Answer
Answer: b [Reason:]
6. The algorithm to remove and place new contents into the cache is called _______
a) Replacement algorithm
b) Renewal algorithm
c) Updation
d) None of the mentioned
Answer
Answer: a [Reason:]
7. The write-through procedure is used
a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
d) None of the mentioned
Answer
Answer: c [Reason:]
8. The bit used to signify that the cache location is updated is ________
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
Answer
Answer: a [Reason:]
9. The copy-back protocol is used
a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
d) None of the mentioned
Answer
Answer: b [Reason:]
10. The approach where the memory contents are transfered directly to the processor from the memory is called ______
a) Read-later
b) Read-through
c) Early-start
d) None of the mentioned
Answer
Answer: c [Reason:]
