Computer Networks MCQ Number 01540

Computer Networks MCQ Set 1

1. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned

Answer

Answer: b [Reason:] The instruction is using immediate addressing mode hence the value is stored in the location 45 is added.

2. In case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache

Answer

Answer: c [Reason:] In this case the operands are implicitly loaded onto the ALU.

3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned

Answer

Answer: b [Reason:] None.

4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode

Answer

Answer: a [Reason:] In this addressing mode, the value of the register serves as another memory location and hence we use pointers to get the data.

5. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]

Answer

Answer: d [Reason:] This instruction is in Base with offset addressing mode.

6. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) direct
d) both Indexed with offset and direct

Answer

Answer: b [Reason:] In this the contents of the PC are directly incremented.

7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations

a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3

Answer

Answer: d [Reason:] In case of, auto increment the increment is done afterwards and in auto decrement the decrement is done first.

8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative

Answer

Answer: a [Reason:] None.

9. The effective address of the following instruction is, MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2].
d) 5*([R1]+[R2])

Answer

Answer: c [Reason:] The addressing mode used is base with offset and index.

10. _____ addressing mode is most suitable to change the normal sequence of execution of instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate

Answer

Answer: a [Reason:] The relative addressing mode is used for this since it directly updates the PC.

Computer Networks MCQ Set 2

1. ARM stands for _____________
a) Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines

Answer

Answer: b [Reason:] ARM is a type of system architecture.

2. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management

Answer

Answer: a [Reason:] The Stand alone feature of the ARM processors is that they’re economically viable.

3. ARM processors where basically designed for _______
a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers

Answer

Answer: c [Reason:] These ARM processors are designed for handheld devices.

4. The ARM processors doesn’t support Byte address ability ?
a) True
b) False

Answer

Answer: b [Reason:] The ability to store data in the form of consecutive bytes.

5. The address space in ARM is ______
a) 2²⁴
b) 2⁶⁴
c) 2¹⁶
d) 2³²

Answer

Answer: d [Reason:] None.

6. The address system supported by ARM systems is/are ______
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian

Answer

Answer: d [Reason:] The way in which, the data gets stored in the system or the way of address allocation is called as address system.

7. Memory can be accessed in ARM systems by _____ instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i,ii,iii
b) i,ii
c) i,iv,v
d) iii,iv,v

Answer

Answer: b [Reason:] None.

8. RISC stands for _________
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer

Answer

Answer: c [Reason:] This is a system architecture, in which the performance of the system is improved by reducing the size of the instruction set.

9. In ARM, PC is implemented using ____
a) Caches
b) Heaps
c) General purpose register
d) Stack

Answer

Answer: c [Reason:] PC is the place where the next instruction about to be executed is stored.

10. The additional duplicate register used in ARM machines are called as _______
a) Copied-registers
b) Banked registers
c) EXtra registers
d) Extential registers

Answer

Answer: b [Reason:] The duplicate registers are used in situations of context switching.

11. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned

Answer

Answer: a [Reason:] When switching from one mode to another, instead of storing the register contents somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual registers.

12. Each instruction in ARM machines is encoded into ____ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte

Answer

Answer: c [Reason:] The data is encrypted to make them secure.

13. All instructions in ARM are conditionally executed.
a) True
b) False

Answer

Answer: a [Reason:] None.

14. The addressing mode where the EA of the operand is the contents of Rn is ______
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
d) None of the mentioned

Answer

Answer: c [Reason:] None.

15. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is _______
a) EA = [Rn].
b) EA = [Rn + Rm].
c) EA = [Rn] + Rm
d) EA = [Rm] + Rn

Answer

Answer: a [Reason:] Effective address is the address that the computer acquires from the current instruction being executed.

Computer Networks MCQ Set 3

1. ____ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter

Answer

Answer: c [Reason:] The assembler is a software used to convert the programs into machine instructions.

2. The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned

Answer

Answer: a [Reason:] This OP – codes tell the system what operation to perform on the operands.

3. The alternate way of writing the instruction, ADD #5,R1 is ______
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way

Answer

Answer: b [Reason:] The ADDI instruction, means the addition is in immediate addressing mode.

4. Instructions which wont appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives

Answer

Answer: d [Reason:] The directives help the program in getting compiled and hence wont be there in the object code.

5. The assembler directive EQU, when used in the instruction : Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum

Answer

Answer: b [Reason:] This basically is used to replace the variable with a constant value.

6. The purpose of the ORIGIN directive is __________
a) To indicate the starting position in memory, where the program block is to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used

Answer

Answer: a [Reason:] This does the function similar to the main statement.

7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU

Answer

Answer: c [Reason:] None.

8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve

Answer

Answer: d [Reason:] This instruction is used to allocate a block of memory and to store the object code of the program there.

9. _____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate

Answer

Answer: b [Reason:] This instruction directive is used to terminate the program execution.

10. The last statement of the source program should be _______
a) Stop
b) Return
c) OP
d) End

Answer

Answer: d [Reason:] This enables the processor to load some other process.

11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive

Answer

Answer: c [Reason:] When the assembler comes across the branch code, it immediately finds the branch offset and replaces it with it.

12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned

Answer

Answer: b [Reason:] The table where the assembler stores the variable names along with their corresponding memory locations and values.

13. The assembler stores the object code in ______
a) Main memory
b) Cache
c) RAM
d) Magnetic disk

Answer

Answer: d [Reason:] After compiling the object code, the assembler stores it in the magnetic disk and waits for further execution.

14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker

Answer

Answer: a [Reason:] The program which is used to load the program into memory.

15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler

Answer

Answer: d [Reason:] This creates entries into the symbol table first and then creates the object code.

Computer Networks MCQ Set 4

1. The master indicates that the address is loaded onto the BUS,by activating _____ signal.
a) MSYN
b) SSYN
c) WMFC
d) INTR

Answer

Answer: a [Reason:] The signal activated by the master in the asynchronous mode of transmission is used to intimate the slave the required data is on the BUS.

2. The devices with variable speeds are usually connected using asynchronous BUS.
a) True
b) False

Answer

Answer: a [Reason:] The devices with variable speeds are connected using asynchronous BUS, as the devices share a master-slave relationship.

3. The MSYN signal is initiated
a) Soon after the address and commands are loaded
b) Soon after the decoding of the address
c) After the slave gets the commands
d) None of the mentioned

Answer

Answer: b [Reason:] This signal is activated by the master to tell the slave that the required commands are on the BUS.

4. In IBM’s S360/370 systems _____ lines are used to select the I/O devices.
a) SCAN in and out
b) Connect
c) Search
d) Peripheral

Answer

Answer: a [Reason:] The signal is used to scan and connect to input or output devices.

5. The meter in and out lines are used for
a) Monitoring the usage of devices
b) Monitoring the amount data transfered
c) Measure the CPU usage
d) None of the mentioned

Answer

Answer: a [Reason:] The line is used to monitor the devices usage for a process.

6. MRDC stands for _______
a) Memory Read Enable
b) Memory Ready Command
c) Memory Re-direct Command
d) None of the mentioned

Answer

Answer: b [Reason:] The command is used to initiate a read from memory operation.

7. The BUS that allows I/O,memory and Processor to coexist is _______
a) Artibuted BUS
b) Processor BUS
c) Backplane BUS
d) External BUS

Answer

Answer: c [Reason:] None.

8. The transmission on the asynchronous BUS is also called as _____
a) Switch mode transmission
b) Variabel transfer
c) Bulk transfer
d) Hand-Shake transmission

Answer

Answer: d [Reason:] The asynchronous transmission is termed as Hand-Shake transfer because the master intimates the slave after each step of the transfer.

9. Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.
a) True
b) False

Answer

Answer: a [Reason:] This mode of transmission is suitable for multiple device situation as it supports variable speed transfer.

10. The asynhronous BUS mode of transmission allows for a faster mode of data transfer.
a) True
b) False

Answer

Answer: b [Reason:] None.

Computer Networks MCQ Set 5

1. The Reason for the disregarding of the SRAM’s is ________
a) Low Efficiency
b) High power consumption
c) High Cost
d) All of the mentioned

Answer

Answer: c [Reason:] The reason for the high cost of the SRAM is because of the usage of more number of transistors.

2. The disadvantage of DRAM over SRAM is/are _______
a) Lower data storage capacities
b) Higher heat descipation
c) The cells are not static
d) All of the mentioned

Answer

Answer: c [Reason:] This means that the cells wont hold their state indefinetly.

3. The reason for the cells to lose their state over time is
a) The lower voltage levels
b) Usage of capacitors to store the charge
c) Use of Shift registers
d) None of the mentioned

Answer

Answer: b [Reason:] Since capacitors are used the charge descipates over time.

4. The capacitors lose the charge over time due to
a) The leakage resistance of the capacitor
b) The small current in the transistor after being turned on
c) The defect of the capacitor
d) None of the mentioned

Answer

Answer: a [Reason:] The capacitor loses charge due to the backward current of the transistro and due to the small resistance.

5. _________ circuit is used to restore the capacitor value.
a) Sense amplify
b) Signal amplifier
c) Delta modulator
d) None of the mentioned

Answer

Answer: a [Reason:] The sense amplifier detects if the value is above or below the threshlod and then restores it.

6. To reduce the number of external connections reqiured, we make use of ______
a) De-multiplexer
b) Multiplexer
c) Encoder
d) Decoder

Answer

Answer: b [Reason:] We multiplex the various address lines onto fewer pins.

7. The processor must take into account the delay in accessing the memory location, such memories are called ______
a) Delay integrated
b) Asynchronous memories
c) Synchronous memories
d) Isochronous memories

Answer

Answer: b [Reason:] None.

8. To get the row address of the required data ______ is enabled.
a) CAS
b) RAS
c) CS
d) Sense/write

Answer

Answer: b [Reason:] This makes the contents of the row required refreshed.

9. In order to read multiple bytes of a row at the same time, we make use of ______
a) Latch
b) Shift register
c) Cache
d) Memory extension

Answer

Answer: a [Reason:] The latch makes it easy to ready multiple bytes of data of the same row simulteneously by just giving the consecutive column address.

10. The block transfer capability of the DRAM is called ________
a) Burst mdoe
b) Block mode
c) Fast page mode
d) Fast frame mode

Answer

Answer: c [Reason:] None.