VLSI MCQ Set 1
1. Inverters are essential for
a) NAND gates
b) NOR gates
c) sequential circuits
d) all of the mentioned
Answer
Answer: d [Reason:] Inverters are needed for restoring logic levels for NAND and NOR gates, sequential and memory circuits.
2. In basic inverter circuit, ______ is connected to ground
a) source
b) gates
c) drain
d) resistance
Answer
Answer: a [Reason:] A basic inverter circuit consists of transistor with source connected to ground and a load resistor connected from drain to positive supply rail Vdd.
3. In inverter circuit, ________ transistors is used as load
a) enhancement mode
b) depletion mode
c) all of the mentioned
d) none of the mentioned
Answer
Answer: b [Reason:] Depletion mode transistors are preferred to be used as load in inverter circuits as it occupies lesser area and are produced on silicon sibstrate unlike resistors.
4. For depletion mode transistor, gate should be connected to
a) source
b) drain
c) ground
d) positive voltage rail
Answer
Answer: a [Reason:] For the depletion mode transistor, gate is connected to source so it is always on and only the characteristic curve Vgs=0 is relevant.
5. In nMOS inverter configuration depletion mode device is called as
a) pull up
b) pull down
c) all of the mentioned
d) none of the mentioned
Answer
Answer: a [Reason:] In nMOS inverter configuration, depletion mode devices are called as pull up and enhancement mode devices are called as pull down transistor.
6. How is nMOS inverter represented?
a) 
b) 
c) 
d) 
Answer
Answer: b [Reason:] nMOS inverter can be represented using two transistors, depletion mode pMOS transistor followed by nMOS transistor. Input is given to the nMOS.
7. The ratio of Zp.u/Zp.d is given by
a) 1/4
b) 4/1
c) 1/2
d) 2/1
Answer
Answer: b [Reason:] The ratio of Zp.u/Zp.d where Z is determined by the length to width ratio of the transistor, is given by 4/1.
8. Pass transistors are transistors used as
a) switches connected in series
b) switches connected in parallel
c) inverters used in series
d) inverter used in parallel
Answer
Answer: a [Reason:] Pass transistors are transistor used as switches in series with lines carrying logic levels due to its isolated nature of the gate.
9. An inverter driven through one or more pass transistors has Zp.u/Zp.d ratio of
a) 1/4
b) 4/1
c) 1/8
d) 8/1
Answer
Answer: d [Reason:] An inverter driven directly from output of another has the ratio of 4/1 and if driven through one or more pass transistors has the ratio of 8/1.
10. In depletion mode pull-up, dissipation is high since current flows when
a) Vin = 1
b) Vin = 0
c) Vout = 1
d) Vout = 0
Answer
Answer: a [Reason:] In nMOS depletion mode pull-up, dissipation is high since current flows Vin = logical 1.
11. In complementary transistor pull-up, current flows when
a) Vin = 1
b) Vin = 0
c) current doesn’t flow
d) Vout = Vin
Answer
Answer: c [Reason:] In complementary transistor pull-up no current flows either for logical 1 or 0, full logical 1 and 0 levels are presented at the output.
VLSI MCQ Set 2
1. Noise Margin is :
a) Amount of noise the logic circuit can withstand
b) Difference between VOH and VIH
c) Difference between VIL and VOL
d) All of the Mentioned
Answer
Answer: d [Reason:] Noise Margin is defined as the amount of noise the logic circuit can withstand, it is given by difference between VOH and VIH or VIL and VOL.
2. The VIL is found from transfer characteristic of inverter by:
a) The point where straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned
Answer
Answer: b [Reason:] The VIL is the input voltage at which the slope of the transition will be equal to -1.
3. The VIH is found from transfer characteristic of inverter by:
a) The point where straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned
Answer
Answer: b [Reason:] The VIH is the input voltage at which the slope of the transition will be equal to -1. In Transfer characteristics at 2 points we will find the slope to be -1.
4. The relation between threshold voltage and Noise Margin is:
a) Vth = sqrt(Noise Margin)
b) Vth = NMH – NML
c) Vth = (NMH+NML)/2
d) None of the metioned
Answer
Answer: d [Reason:] None.
5. The Lower Noise Margin is given by:
a) VOL – VIL
b) VIL – VOL
c) VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater)
d) All of the Mentioned
Answer
Answer: b [Reason:] Noise margin = VIL-VOL.
6. The Higher Noise Margin is given by:
a) VOH – VIH
b) VIH – VOH
c) VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
d) All of the mentioned
Answer
Answer: a [Reason:] Noise margin =VOH – VIH.
7. The Uncertain or transition region is between:
a) VIH and VOH
b) VIL and VOL
c) VIH and VIL
d) VOH and VOL
Answer
Answer: c [Reason:] In Input the uncertain region is VIH and VIL.
8. The noise immunity ____________ with noise margin
a) Decreases
b) Increases
c) Constant
d) None of the Mentioned
Answer
Answer: b [Reason:] The noise immunity is directly proportional to noise margin.
9. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer
Answer: c [Reason:] Logic output 0 from first gate is considered as logic input 0 at second gate as it lies within the range.
10. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer
Answer: b [Reason:] The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.
11. Input Voltage between VIL and VOL is considered as:
a) Logic Input 1
b) Logic Input 0
c) Uncertain
d) None of the mentioned
Answer
Answer: b [Reason:] None.
12. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output 0 from the 1st gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer
Answer: b [Reason:] The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.
13. Determine the Noise Margin for 5V TTL inverter gate:
a) NMH = 0.4V and NML =0.4V
b) NMH = 2.4V and NML = 0.4V
c) NMH = 2V and NML = 0.8V
d) NMH = 1.5V and NML = 0.4V
Answer
Answer: a [Reason:] None.
14. Determine the Noise Margin for 5V CMOS inverter gate:
a) NMH = 1V and NML = 1V
b) NMH = 3.7V and NML = 0.2V
c) NMH = 0.9V and NML = 1V
d) NMH = 0.2V and NML =0.5V
Answer
Answer: c [Reason:] None.
15. Noise margin of CMOS is :
a) Better than TTL and ECL
b) Less than TTL and ECL
c) Equal to TTL and ECL
d) None of the Mentioned
Answer
Answer: a [Reason:] None.
VLSI MCQ Set 3
1. Pseudo random testing can determine test length.
a) true
b) false
Answer
Answer: a [Reason:] Pseudo ramdom testing can also determine the relationship between test confidence, fault coverage, fault detectability and test length can also be determined.
2. The pseudo-random testing has
a) high cost
b) less development time
c) low cost but more testing time
d) low cost and less testing time
Answer
Answer: b [Reason:] Pseudo random testing method has less development time and low development cost. This can be balanced with increased test length.
3. In pseudo-random testing, the test length should be ________ the exhaustive test
a) lesser than
b) greater than
c) more than
d) none of the mentioned
Answer
Answer: a [Reason:] In pseudo-random testing, the test length should be less than that of the exhaustive test (its upper bound) or the test length will be prohibited for most circuits. This makes the pseudo-random testing practical.
4. Pseudo-random testing method involves
a) homogeneous bernoulli process
b) non homogeneous bernoulli process
c) repeatable bernoulli process
d) non repeatable bernoulli process
Answer
Answer: b [Reason:] The most accurate method invlolved in test pattern generation is non homogeneous bernoulli process. This is called as pseudo random testing method.
5. Which method is more accurate?
a) pseudo-random testing
b) random testing
c) LFSR
d) cellular automata
Answer
Answer: a [Reason:] Pseudo-random testing method gives more accurate results than random testing method. Its test length estimation is smaller and test quality is better.
6. The fault coverage in a pseudo random test is determined using
a) fault detection
b) fault removal
c) fault simulation
d) fault distribution
Answer
Answer: c [Reason:] The fault coverage in a pseudo random test can be determined by using fault simulation. The fault coverage is the the measure used to rate the algorithmically generated tst set.
7. Faults causing largest loss of coverage is those with
a) smallest detectability
b) largest detectability
c) all of the mentioned
d) none of the mentioned
Answer
Answer: a [Reason:] Faults causing largest loss of coverage is those with smallest detectability. These faults are counted in the initial nonzero elements of the detectability profile.
8. With test sequence of length zero, fault coverage is
a) maximum
b) 1
c) 0
d) cannot be determined
Answer
Answer: c [Reason:] With test sequence of length zero, the fault coverage is 0 and each fault is responsible for fault coverage loss regardless of its detectability.
9. Upper bound fault is the fault with detectability
a) 0
b) 1
c) maximum
d) minimum
Answer
Answer: b [Reason:] Upper bound fault is the fault with detectability k=1 and it is used where the detectability profile of the circuit under test is unknown.
10. To reduce the size mismatch, test length is minimized.
a) true
b) false
Answer
Answer: a [Reason:] If the size of pseudo-random test generator does not match with the size of circuit under test, size mismatch occurs. This can be comprimised by reducing the test length.
VLSI MCQ Set 4
1. Primitive polynomial should have minimum number of zero coefficient.
a) true
b) false
Answer
Answer: a [Reason:] Primitive polynomials with minimum number of zero coefficients are the desired characteristic polynomail for the LFSR.
2. The minimum number of EX-OR gates used is in between
a) 0 to 2
b) 1 to 3
c) 2 to 5
d) 3 to 7
Answer
Answer: b [Reason:] The minimum number of EX-OR gates used for the linear feedback shift register is in between 1 and 3.
3. The LFSR takes reasonable time if the n value is
a) below 50
b) below 100
c) below 10
d) below 25
Answer
Answer: d [Reason:] The LFSR’s degree value is limited to 22 to 25 for producing maximal length sequence in reasonable amount of time.
4. Which is used to initialize the LFSRs?
a) zeroes
b) ones
c) preset of flip-flop
d) EX-OR gate
Answer
Answer: c [Reason:] The preset of each flip-flop in LFSR to used to initialize the LFSRs and initial non-zero coeeficient or state ensures maximal length sequence is obtained.
5. The beginning and end of the maximal length sequence can be determined using
a) AND gate
b) NAND gate
c) AND or NAND gate
d) both AND and NAND gate
Answer
Answer: c [Reason:] The beginning and end of the maximal length sequence of the LFSR can be determined using AND gate or NAND gate.
6. Preloading different starting value for the LFSR is called as
a) seeding
b) reseeding
c) deseeding
d) pre-seeding
Answer
Answer: b [Reason:] Initializing with a specific value to the LFSR is called as seeding and preloading different starting value is called as reseeding.
7. The primitive polynomial has a property according to which the runs of 1s ______ to runs of 0s
a) equal
b) greater
c) lesser
d) not related
Answer
Answer: a [Reason:] The primitive polynomial has a property of randomness according to which the runs of 1s equal to runs of 0s.
8. The total number of runs is given mathematically as
a) 2n
b) 2(n-1)
c) 2(n+1)
d) 2n-1
Answer
Answer: b [Reason:] The total number of runs is given as 2(n-1) which is the total number of transitions from 1 to 0 or from 0 to 1.
9. ______ of the runs will have a length of 1
a) one third
b) one fourth
c) half
d) one eight
Answer
Answer: c [Reason:] The length of the runs are distributed as – half of the runs have length 1, quarter with length 2, a eight length 3 and a sixteenth length 4 and so on.
10. The length of the runs is dependent on whether the LFSR is internal or external feedback.
a) true
b) false
Answer
Answer: b [Reason:] The length of the run is independent of whether the LFSR is internal or external feedback and LFSR is also known as pseudo random pattern generator.
11. Which process is used to develop LFSR method?
a) random method
b) gaussian method
c) deterministic method
d) bernoulli method
Answer
Answer: d [Reason:] Bernoulli method is used in modelling the linear feedback shift register testing method and this is called as random pattern generation method.
VLSI MCQ Set 5
1. Reduction in power dissipation can be brought by
a) increasing transistor area
b) decreasing transistor area
c) increasing transistor feature size
d) decreasing transistor feature size
Answer
Answer: a [Reason:] The 3:1 reduction in power dissipation can be brought at the expense of increasing the transistor area by 50%.
2. When does longest delay occur in 8:1 inverters?
a) during 1 to 0 transition
b) during 0 to 1 transition
c) during faster speed
d) delays are always short
Answer
Answer: b [Reason:] In 8:1 inverters, longest delay will occur when the output of the first stage is changing from logic 0 to 1 and capacitance must charge through pull-up resistance.
3. In inverter during logic 1 to 0 transition, capacitance discharges at
a) pull-up resistance
b) pull-down resistance
c) both pull-up and pull-down
d) at gate
Answer
Answer: b [Reason:] During the logic 1 to 0 transition, the capacitance which is charged through pull-up must always discharge through pull-down transistor at first stage.
4. In minimum size nMOS 8:1 inverter the logic 0 to 1 transition delay is given as
a) 5Ʈ
b) 20Ʈ
c) 40Ʈ
d) 50Ʈ
Answer
Answer: c [Reason:] For minimum pull-down feature size nMOS 8:1 inverter, the logic 0 to 1 transition delay can be given as 8Rs x 5 square Cg which gives 40Ʈ.
5. In minimum size nMOS 8:1 inverter the logic 1 to 0 transition delay is given as
a) 5Ʈ
b) 20Ʈ
c) 40Ʈ
d) 50Ʈ
Answer
Answer: a [Reason:] 8:1 nMOS inverter allows stray and wiring capacitance and the logic 1 to 0 transition delay can be given as 1Rs x 5 square Cg which gives 5Ʈ.
6. For a regular 8:1 inverter the transition delay is given as
a) 10Ʈ
b) 20Ʈ
c) 21Ʈ
d) 25Ʈ
Answer
Answer: c [Reason:] For 8:1 inverter the logic 0 to 1 transition delay can be given as 21Ʈ and logic 1 to 0 transition delay can be given as 2(1/3)Ʈ .
7. The area of CMOS inverter is proportional to
a) area of n device
b) area of p device
c) total area of n and p device
d) square of minimum feature size
Answer
Answer: c [Reason:] The area of a basic CMOS inverter is proportional to the total area occupied bu the p and n devices (WpLp + WnLn).
8. The ratio of Wp/Wn can be given as
a) 1:2
b) 2:1
c) 1:1
d) 2:2
Answer
Answer: c [Reason:] Minimum area can be achieved by choosing minimum dimensions for Wp, Wn, Lp, Ln which is 2λ and the ratio of Wp/Wn can be given as 1:1.
9. Switching power dissipation can be given as
a) Cl x Vdd x f
b) Vdd2 x f
c) Cl x Vdd2
d) Cl x Vdd2 x f
Answer
Answer: d [Reason:] Switching power dissipation Psd can be given as Cl x Vdd2 x f where Cl is load capacitance, Vdd is power supply voltage and f is the frequency of switching.
10. Load capacitance can be minimized by
a) increasing A
b) decreasing A
c) increasing Psd
d) does not depend on A
Answer
Answer: b [Reason:] For fixed Vdd and f, minimizing Psd requires minimizing Cl which can be minimized by decreasing area A as it is directly proportional to gate area.
11. Rise time and fall time can be equalized by
a) βn = βp
b) βn = 2βp
c) βp = 2βn
d) βn = 1/2βp
Answer
Answer: a [Reason:] Rise time tr and fall time tf can be equalized by using βn = βp, which requires (Wp/Lp) = (µn/µp)(Wn/Ln).
