VLSI MCQ Set 1
1. The electrical equivalent component for MOS structure is:
a) Resistor
b) Capacitor
c) Inductor
d) Switch
Answer
Answer: b [Reason:] The MOS structure acts as a capacitor with metal gate and semiconductor acting as parallel plate conductors and oxide as dielectric between them.
2. The Fermi potential is the function of:
a) Temperature
b) Doping concentration
c) Difference between Fermi level and intrinsic Fermi level
d) All of the mentioned
Answer
Answer: d [Reason:] The Fermi potential, which is a function of temperature and doping, denotes the difference between the intrinsic Fermi level and the Fermi level.
3. The direction of electric field when the gate voltage is zero:
a) Metal to semiconductor
b) Semiconductor to metal
c) No electric field exists
d) None of the mentioned
Answer
Answer: a [Reason:] Metal being more positive compared to semiconductor.. Electric field exists from metal to semiconductor.
4. Consider a MOS structure with equilibrium Fermi potential of the doped silicon substrate is given as 0.3eV. Electron affinity of Si is 4.15eV and metal is 4.1eV. Find the built in potential of the MOS system:
a) -0.8eV
b) 0.8eV
c) 0.9eV
d) -0.9eV
Answer
Answer: d [Reason:] Surface potential: qΦs = 4.15eV+0.55eV+0.3eV=5.0eV
qΦm-qΦs = 4.1eV – 5.0eV =-0.9eV.
5. When gate voltage is negative for enhancement mode n-MOS, the direction of electric field will be:
a) Metal to semiconductor
b) Semiconductor to metal
c) No field exists
d) None of the mentioned
Answer
Answer: b [Reason:] When gate voltage is negative, holes in substrate are attracted towards surface creating electric field from semiconductor to metal.
6. At threshold Voltage, the surface potential is:
a) – Fermi potential
b) Fermi potential
c) 2 Fermi potential
d) -2 Fermi potential
Answer
Answer:a [Reason:] When surface potential reaches –fermi potential, the surface inversion occurs. The gate voltage which brings these changes is known as threshold voltage.
7. Surface inversion occurs when gate voltage is:
a) Less than zero
b) Less than threshold voltage
c) Equal to threshold voltage
d) Greater than threshold voltage
Answer
Answer: c [Reason:] Surface inversion occurs when gate voltage is equal to threshold voltage.
8. The energy band diagram of the MOS system when gate voltage is zero is:
a) 
b) 
c) 
d) 
Answer
Answer: a [Reason:] The energy band diagram of enhancement mode nMOSFET when gate voltage is zero is :
9. For enhancement mode n-MOSFET, the threshold voltage is:
a) Equal to 0
b) Greater than zero or Positive quantity
c) Negative voltage or lesser than zero
d) All of the mentioned
Answer
Answer: b [Reason:] For enhancement mode n-MOSFET, the threshold voltage is positive quantity.
10. The threshold voltage depends on:
a) The workfunction difference between gate and channel
b) The gate voltage component to change surface potential
c) The gate voltage component to offset the depletion charge and fixed charges in gate oxide
d) All of the mentioned
Answer
Answer: d [Reason:] The threshold voltage depends on: The workfunction difference between gate and channel, The gate voltage component to change surface potential, The gate voltage component to offset the depletion charge and fixed charges in gate oxide
11. The Energy band diagram of MOS system when gate voltage is equal to threshold voltage is:
a) 
b) 
c) 
d) 
Answer
Answer: c [Reason:] The Energy band diagram of MOS system when gate voltage is equal to threshold voltage is
12. The expression for threshold voltage for the enhancement mode nMOSFET is :
a) Φgc-2ϕf-Qbo/Cox-Qox/Cox
b) Φgc+ϕf-Qbo/Cox
c) Φgc-ϕf-Qbo/Cox+Qox/Cox
d) Φgc+2ϕf-Qbo/Cox-Qox/Cox
Answer
Answer: a [Reason:] The expression for threshold voltage for the enhancement mode nMOSFET is Φgc-2ϕf-Qbo/Cox-Qox/Cox
VLSI MCQ Set 2
1. Multipliers are built using
a) binary adders
b) binary subtractors
c) dividers
d) multiplexers
Answer
Answer: a [Reason:] A multiplier is an electronic circuit used to multiply two bianry numbers. It is built using binary adders that is full adders.
2. Which method uses reduced number of partial products?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
Answer
Answer: d [Reason:] Multiplication in multipliers is done by obtaining partial products and then summing it up. Modified booth encoding reduces the number of partial products that must be summed.
3. Which method is easier to manipulate accumulator content?
a) left shifting
b) right shifting
c) serial shifting
d) parallel shifting
Answer
Answer: b [Reason:] It is easier to right shift the contents of accumulator than to left shift. This can be used to eliminate the least significant bits of the product.
4. Which multiplier is very well suited for twos complement numebers?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
Answer
Answer: a [Reason:] Baugh-wooley method is used to design multipliers that are regular in structure and is very well suited for twos complement numbers.
5. What is the delay required to perform a single operation in pipelined structure?
a) 2n
b) 3n
c) 4n
d) n
Answer
Answer: b [Reason:] The delay of one operation through the pipeline is 3n that is it takes 3n clock cycles to obtain a product after X and Y are input.
6. Latches choosen are
a) static shift registers
b) any flipflop
c) dynamic shift register
d) multiplexers
Answer
Answer: c [Reason:] The latches choosen are dynamic shift register as the structure will be continuously clocked.
7. Which method reduces number of cycles of operation?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
Answer
Answer: d [Reason:] Modified booth encoding algorithm avoids many idle cells in a cellular multiplier as well as reduces the number of cycles compared with the serial-parallel multiplier.
8. The completion time for multiplication time in baugh-wooley method is
a) n
b) 2n
c) 3n
d) 4n
Answer
Answer: b [Reason:] The completion time for multiplication in Braun or Baugh-wooley is proportional to 2n where as completion time in Wallace tree method is proportional to log(base 2)(n).
9. In which method minimum number of adder cells are used?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
Answer
Answer: c [Reason:] Dadda multipliers are similar to Wallace trees but it has reduced number of adder cells. This is a technique developed from Wallace tree but with an improvement.
10. Which method is suitable for larger operands?
a) baugh-wooley algorithm
b) wallace trees
c) dadda multipliers
d) modified booth encoding
Answer
Answer: b [Reason:] Wallace tree multipliers should be used for larger operands and where the performance is critical.
VLSI MCQ Set 3
1. The n-MOS invertor is better than BJT in terms of:
a) Fast switching time
b) Low power loss
c) Smaller overall layout area
d) All the the mentioned
Answer
Answer : d [Reason:] The n-MOS invertor is better than BJT invertor due to fast switching time, low power loss, smaller overall layout area.
2. The n-MOS invertor consists of n-MOS transistor as driven and
a ) Resistor as a load
b ) Depletion mode n-MOS as a load
c) Enhancement mode n-MOS as a load
d) Any of the mentioned
Answer
Answer: d [Reason:] the n-MOS inverter consists of n-MOS and resistor or depletion mode n-MOS or enhancement mode n-MOS at the pull up load.
3. If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured at:
a) Source of the both transistor
b) Drains of the both transistor
c) Drain of n-MOS and source of p-MOS
d) Source of n-MOS and drain of p-MOS
Answer
Answer: a [Reason:] When the transistors are interchanged, The drain of n-MOS is connected to supply voltage, drain of p-MOS is connected to ground . The output is measured at source of both the transistors.
4. What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS inverter circuit are exchanged?
a) Output is same
b) Output is reversed
c) Output is always high
d) Output is always low
Answer
Answer: b [Reason:] When the input is low, p-MOS is ON and the output is pulled down to the ground. When the input is high, n-MOS is ON and the output is pulled up to the supply voltage.
5. The average power dissipated in resistive load n-MOS inverter is:
a) 0
b) VDD (VDD-VOL)/R
c) VDD (VDD-VOL)/2R
d) VDD (VDD-VIH)/2R
Answer
Answer: c [Reason:] When the input voltage is equal to VOH on the other hand, both the driver MOSFET and the load resistor conduct a nonzero current. Since the output voltage in this case is equal to VOL, DC power consumption of the inverter can be estimated as VDD.(VDD-VOL)/2R
6. The depletion mode n-MOS as an active load is better than enhancement load n-MOS in:
a) Sharp VTC transition and better noise margins
b) Single power supply
c) Smaller overall layout area
d) All of the mentioned
Answer
Answer : d [Reason:] The depletion mode n-MOS transistor as load requires single power supply, smaller overall layout area, and sharp VTC transition.
7. The enhancement mode n-MOS load inverter requires 2 different supply voltages to:
a) Keep load transistor in cutoff region
b) Keep load transistor in linear region
c) Keep load transistor in saturation region
d) None of the mentioned
Answer
Answer: b [Reason:] The enhancement mode n-MOS load inverter requires 2 different supply voltages to keep load transistor in linear region.
8. The CMOS inverter consist of:
a) Enhancement mode n-MOS transistor and depletion mode p-MOS transistor
b) Enhancement mode p-MOS transistor and depletion mode n-MOS transistor
c) Enhancement mode p-MOS transistor and enhancement mode p-MOS transistor
d) Enhancement mode p-MOS transistor and enhancement mode n-MOS transistor
Answer
Answer: d [Reason:] The CMOS inverter consist of enhancement mode p-MOS and enhancement mode n-MOS.
9. In the CMOS inverter the output voltage is measured across:
a) Drain of n-MOS transistor and ground
b) Source of p-MOS transistor and ground
c) Source of n-MOS transistor and source of p-MOS transistor
d) Gate of p-MOS transistor and Gate of n-MOS transistor
Answer
Answer: a [Reason:] In the CMOS inverter the output voltage is measured across Drain of n-MOS transistor and ground.
10. When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the transistors are operating in:
a) N-MOS is cutoff, p-MOS is in Saturation
b) P-MOS is cutoff, n-MOS is in Saturation
c) Both the transistors are in linear region
d) Both the transistors are in saturation region
Answer
Answer : d [Reason:] When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, both the transistors are operating in saturation region
11. The switching threshold voltage VTH for an ideal inverter is equal to:
a) (VDD-VOL)/2
b) VDD
c) (VDD)/2
d) 0
Answer
Answer: c [Reason:] The switching threshold voltage VTH for an ideal inverter is equal to (VDD)/2
12. Which of these invertors is more efficient?
a) Depletion mode n-MOS inverter
b) pMOS inverter
c) CMOS inverter
d) Resistive load nMOS inverter
Answer
Answer: c [Reason:] The power loss in CMOS inverter is very small and the I-V characteristics is approximately equal to ideal inverter. Therefore the CMOS inverter is most efficient.
VLSI MCQ Set 4
1. Lithography is:
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip
Answer
Answer: a [Reason:] Lithography is the process used to develop a pattern to a layer on the chip.
2. Silicon oxide is patterned on a substrate using:
a) Physical lithography
b) Photolithography
c) Chemical lithography
d) Mechanical lithography
Answer
Answer: b [Reason:] Silicon oxide is patterned on a substrate using Photolithography.
3. Positive photo resists are used more than negative photo resists because:
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution
is not as high as that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution
is not as high as that of the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light
Answer
Answer: a [Reason:] Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists. Therefore, negative photo resists are-used less commonly in the manufacturing of high-density integrated circuits.
4. The ______ is used to reduce the resistivity of poly silicon:
a) Photo resist
b) Etching
c) Doping impurities
d) None of the mentioned
Answer
Answer: c [Reason:] The resistivity of poly silicon is reduced by Doping impurities.
5. The isolated active areas are created by technique known as:
a) Etched field-oxide isolation
b) Local Oxidation of Silicon
c) Both the mentioned
d) None of the mentioned
Answer
Answer: c [Reason:] To create isolated active areas both the techniques can be used. Among them Local Oxidation of Silicon(LOCOS) is most efficient.
6. The chemical used for shielding the active areas to achieve selective oxide growth is:
a) Silver Nitride
b) Silicon Nitride
c) Hydrofluoric acid
d) Polysilicon
Answer
Answer: b [Reason:] Selective oxide growth is achieved by shielding the active areas. Silicon nitride (Si3N4) is used for shielding the active areas during oxidation, which effectively inhibits oxide growth.
7. The dopants are introduced in the active areas of silicon by:
a) Diffusion process
b) Ion Implantaion process
c) Chemical Vapour Deposition
d) Either Diffusion or Ion Implantaion Process
Answer
Answer: d [Reason:] Two ways to add dopants are diffusion and ion implantation.
8. To grow the polysilicon gate layer, the chemical used for chemical vapour deposition is:
a) Silicon Nitride(Si4N3)
b) Silane gas(SiH4 )
c) Silicon oxide
d) None of the mentioned
Answer
Answer: b [Reason:] Silicon Wafer is placed in a reactor with silane gas (SiH4), and they are heated again to grow the polysilicon layer by chemical vapor deposition.
9. The process by which Aluminium is grown over the entire wafer , also filling the contact cuts is:
a) Sputtering
b) Chemical vapour deposition
c) Epitaxial growth
d) Ion Implantation
Answer
Answer: a [Reason:] Aluminum is sputtered over the entire wafer, it also fills the contact cuts.
10. The process involved in growing the shaded region is:
a) Chemical vapor deposition (CVD)
b) Sputtering and patterned by etching
c) Chemical vapor deposition (CVD) and patterned by HF acid etching
d) Chemical vapor deposition (CVD) and patterned by dry (plasma) etching
Answer
Answer: d [Reason:] The poly silicon layer is produced using chemical vapor deposition (CVD) and it is patterned by dry (plasma) etching.
11. Chemical Mechanical Polisihing is used to:
a) Remove silicon oxide
b) Remove silicon nitride and pad oxide
c) Remove polysilicon gate layer
d) Reduce the size of the layout
Answer
Answer: b [Reason:] The pad oxide and nitride are removed using a Chemical Mechanical Polishing (CMP) step.
12.
Gate oxide layer consists of:
a) SiO2 layer, overlaid with a few layers of an oxynitrided oxide
b) Only SiO2 Layer
c) SiO2 layer with Polysilicon Layer
d) SiO2 layer and stack of epitaxial layers of Polysilicon
Answer
Answer: a [Reason:]Current processes seldom use a pure SiO2 gate oxide, but prefer to produce a stack that consists of a few atomic layers, each 3–4 Å thick, of SiO2 for reliability, overlaid with a few layers of oxy-nitrided oxide (one with nitrogen added).
13. What is Piranha Solution
a) It is a 3:1 to 5:1 mix of nitric acid and hydrogen peroxide that is used to develop the oxide layer on silicon substrate
b) It is a 3:1 to 5:1 mix of sulphuric acid and hydrofluoric acid that is used to clean silicon wafers removing organic and metal contaminants or photo resist after metal patterning
c) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to grow the oxide layer on the silicon
d) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to clean wafers of organic and metal contaminants or photo resist after metal patterning
Answer
Answer: d [Reason:] Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen-peroxide that is used to clean silicon wafers of metal and organic contaminants or photo-resist after metal patterning.
VLSI MCQ Set 5
1. nMOS fabrication process is carried out in
a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Answer
Answer: a [Reason:] nMOS fabrication process is carried out in thin wafer of a single crystal with high purity.
2. _____ impurities are added to the wafer of the crystal
a) n impurities
b) p impurities
c) siicon
d) crystal
Answer
Answer: b [Reason:] p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.
3. What kind of substrate is provided above the barrier to dopants?
a) insulating
b) conducting
c) silicon
d) semi conducting
Answer
Answer: a [Reason:] Above a layer of silicon dioxide which acts as barrier, insulating layer is provided upon which other layers may be deposited and patterned.
4. The photoresist layer is exposed to
a) visible light
b) ultraviolet light
c) infra red light
d) LED
Answer
Answer: b [Reason:] The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
5. In nMOS device, gate material could be
a) silicon
b) polysilicon
c) boron
d) phosporus
Answer
Answer: b [Reason:] In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.
6. The commonly used bulk substrate in nMOS fabrication is
a) silicon crystal
b) silicon-on-sapphire
c) phosporus
d) silicon-di-oxide
Answer
Answer: c [Reason:] In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-on-sapphire.
7. In nMOS fabrication, etching is done using
a) plasma
b) hydrochloric acid
c) sulphuric acid
d) sodium chloride
Answer
Answer: a [Reason:] In nMOS fabrication, etching is done using hydroflouric acid or plasma. Etching is a process used to remove layers from the surface.
8. Heavily doped polysilicon is deposited using
a) chemical vapour decomposition
b) chemical vapour deposition
c) chemical deposition
d) dry deposition
Answer
Answer: b [Reason:] The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.
9. In diffusion process, ______ impurity is desired
a) n type
b) p type
Answer
Answer: a [Reason:] Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.
10. Contact cuts are made in
a) source
b) drain
c) metal layer
d) diffusion layer
Answer
Answer: a [Reason:] Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made.
11. Interconnection pattern is made on
a) polysilicon layer
b) silicon-di-oxide layer
c) metal layer
d) diffusion layer
Answer
Answer: c [Reason:] The metal layer is masked and etched to form interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.
12. SIlicon-di-oxide is a good insulator.
a) true
b) false
Answer
Answer: a [Reason:] SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of MOS transistor.
13. _______ is used to suppress unwanted conduction
a) phosporus
b) boron
c) silicon
d) oxygen
Answer
Answer: b [Reason:] Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions.
14. Which is used for the interconnection?
a) boron
b) oxygen
c) aluminium
d) silicon
Answer
Answer: c [Reason:] Aluminium is the suitable material used for the circuit interconnection or connecting two layers.
