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# Multiple choice question for engineering

## Set 1

1. The inputs in the PLD is given through
a) NAND gates
b) OR gates
c) NOR gates
d) AND gates

Answer: d [Reason:] The inputs in the PLD is given through AND gate followed by inverting & non-inverting buffer.

2. PAL refers to
b) Programmable Logic Array
c) Programmable Array Logic
d) None of the Mentioned

Answer: c [Reason:] PAL refers to Programmable Array Logic.

3. Outputs of the AND gate in PLD is known as
a) Input lines
b) Output lines
c) Strobe lines
d) None of the Mentioned

Answer: b [Reason:] Outputs of the AND gate in PLD is known as output lines.

4. PLA contains
a) AND and OR arrays
b) NAND and OR arrays
c) NOT and AND arrays
d) NOR and OR arrays

Answer: a [Reason:] Programmable Logic Array is a type of fixed architecture logic devices with programmable AND gates followed by OR gates.

5. PLA is used to implement
a) A complex sequential circuit
b) A simple sequential circuit
c) A complex combinational circuit
d) A simple combinational circuit

Answer: c [Reason:] Since, PLA is the combination of different gates, flip-flops. So, it is used to implement complex combinational circuit.

6. A PLA is similar to a ROM in concept except that
a) It hasn’t capability to read only
b) It hasn’t capability to read or write operation
c) It doesn’t provide full decoding to the variables
d) It hasn’t capability to write only

Answer: c [Reason:] A PLA is similar to a ROM in concept except that it doesn’t provide full decoding to the variables and doesn’t generate all the minterms as in the ROM.

7. For programmable logic functions, which type of PLD should be used?
a) PLA
b) CPLD
c) PAL
d) SLD

Answer: b [Reason:] Since, PAL is programmable and is fixed and also circuitry working is less.

8. The complex programmable logic device contains several PLD blocks and __________
a) A language compiler
b) AND/OR arrays
c) Global interconnection matrix
d) Field-programmable switches

Answer: c [Reason:] The complex programmable logic device contains several PLD blocks and a global interconnection matrix by which it communicate through several devices.

9. Which type of device FPGA are?
a) SLD
b) SROM
c) EPROM
d) PLD

Answer: d [Reason:] Field-programmable gate arrays (FPGAs) are reprogrammable silicon chips. In contrast to processors that you find in your PC, programming an FPGA rewires the chip itself to implement your functionality rather than run a software application.

10. The difference between a PAL & a PLA is
a) PALs and PLAs are the same thing
b) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane
c) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane
d) The PAL has more possible product terms than the PLA

Answer: b [Reason:] The main difference between a PAL & PLA is that PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane.

11. If a PAL has been programmed once
a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed

Answer: d [Reason:] Since, PAL is dynamic in nature. So, it can’t be reprogrammed.

12. The FPGA refers to
a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array

Answer: b [Reason:] The FPGA refers to Field Programmable Gate Array.

13. The full form of VLSI is
a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) None of the Mentioned

Answer: c [Reason:] The full form of VLSI is Very Large Scale Integration in which FPGA is implemented.

14. In FPGA, vertical and horizontal directions are separated by
a) A line
b) A channel
c) A strobe
d) A flip-flop

Answer: b [Reason:] Vertical and horizontal directions is separated by a channel in an FPGA which determines the location of the output.

15. Applications of PLAs are
a) Registered PALs
b) Configurable PALs
c) PAL programming
d) All of the Mentioned

Answer: d [Reason:] Applications of PLAs are as mentioned above and these are performed by using an extra flip-flop with PAL.

## Set 2

1. What is memory decoding?
a) The process of Memory IC used in a digital system is overloaded with data
b) The process of Memory IC used in a digital system is selected for the range of address assigned
c) The process of Memory IC used in a digital system is selected for the range of data assigned
d) The process of Memory IC used in a digital system is overloaded with data allocated in memory cell

Answer: b [Reason:] The Memory IC used in a digital system is selected or enabled only for the range of addresses assigned to it and this process is called memory decoding.

2. The first step in the design of memory decoder is
a) Selection of a EPROM
b) Selection of a RAM
d) Data insertion

Answer: c [Reason:] The first step in the design of memory decoder is address assignment in non-overlapped manner.

3. How many address bits are required to select memory location in Memory decoder?
a) 4 KB
b) 8 KB
c) 12 KB
d) 16 KB

Answer: c [Reason:] Since, the given EPROM and RAM are of 4 KB (4 * 1024 = 4096) capacity, it requires 12 address bit to select one of the 4096 memory locations.

4. How memory expansion is done?
a) By increasing the supply voltage of the Memory ICs
b) By decreasing the supply voltage of the Memory ICs
c) By connecting Memory ICs together
d) None of the Mentioned

Answer: c [Reason:] Memory ICs can be connected together to expand the number of memory words or the number of bits per word.

5. IC 4116 is organised as
a) 512 * 4
b) 16 * 1
c) 32 * 4
d) 64 * 2

Answer: c [Reason:] IC 4116 is organised as 16 * 1 K which has capability to store 16 KB.

6. To construct 16K * 4-bit memory, how many 4116 ICs are required?
a) 1
b) 2
c) 3
d) 4

Answer: d [Reason:] Since, IC 4116 is organised as 16K * 1. So, four ICs are required for 16K * 4 memory implementation.

7. How many 1024 * 1 RAM chips are required to construct a 1024 * 8 memory system?
a) 4
b) 6
c) 8
d) 12

Answer: c [Reason:] One 1024 * 1 RAM chips is of 1-bit. SO, for construction of 1024 * 8 RAM chip it will require 8 chips.

8. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits?
a) 2
b) 4
c) 6
d) 8

Answer: d [Reason:] 16K * 4 = 64K RAM is of 64K. So, 64 * 8 = 512K. Hence, 512/64 = 8.

9. The full form of PLD is
b) Programmable Logic Data
c) Programmable Logic Devices

Answer: c [Reason:] The full form of PLD is Programmable Logic Devices.

10. PLD contains a large number of
a) Flip-flops
b) Gates
c) Registers
d) All of the Mentioned

Answer: d [Reason:] Programmable Logic Devices is a collection of large number of gates, flip-flops, registers that are interconnected on the chip.

11. Logic circuits can also be designed using
a) RAM
b) ROM
c) PLD
d) PLA

Answer: c [Reason:] PLD has large number of flip-flops. So, logic circuits can be designed using this PLD circuit.

12. In PLD, there are provisions to perform interconnections of the gates internally, because of
a) High reliability
b) High conductivity
c) The desired logic implementation
d) The desired output

Answer: c [Reason:] In PLD, there are provisions to perform interconnections of the gates internally so that the desired logic can be implemented.

13. Why antifuses are implemented in a PLD?
a) To protect from high voltage
b) To increase the memory
c) To implement the programmes
d) As a switching devices

Answer: c [Reason:] Programmings are accomplished by using antifuses in a PLD and it is fabricated at the cross points of the gates.

14. How many types of PLD is?
a) 2
b) 3
c) 4
d) 5

Answer: a [Reason:] There are two types of PLD, viz., devices with fixed architecture and devices with flexible architecture.

15. PLA refers to
b) Programmable Logic Array
c) Programmable Array Logic
d) None of the Mentioned

Answer: c [Reason:] PLA refers to Programmable Logic Array.

## Set 3

1. The time from the beginning of a read cycle to the end of tACS/tAA is called as
a) Write enable time
b) Data hold
d) Access time

Answer: d [Reason:] The time from the beginning of a read cycle to the end of tACS/tAA is called as access time.

2. Why did PROM introduced?
a) To increase the storage capacity
b) To increase the address locations
c) To provide flexibility
d) To reduce the size

Answer: c [Reason:] In order to provide some flexibility in the possible applications of ROM, PROM is introduced.

3. Which of the following is programmed electrically by the user?
a) ROM
b) EPROM
c) PROM
d) EEPROM

Answer: c [Reason:] Programmable ROMs can be programmed electrically by the user but can’t be reprogrammed.

4. PROMs are available in
a) Bipolar and MOSFET technologies
b) MOSFET and FET technologies
c) FET and bipolar technologies
d) MOS and bipolar technologies

Answer: d [Reason:] PROMs are available in both bipolar and MOS (Metal Oxide Semiconductor) technologies.

5. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is
a) 4096
b) 16384
c) 32768
d) 8129

Answer: b [Reason:] 2048 * 8 = 16384 bits.

6. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and a word length of eight bits?
a) Eight
b) Two
c) One
d) Four

Answer: a [Reason:] It is the requirement the word of length 8 bits. So, one word needs of 1 bit and 8 bit requires 8 bits.

7. Which of the following best describes the fusible-link PROM?
a) Manufacturer-programmable, reprogrammable
b) Manufacturer-programmable, one-time programmable
c) User-programmable, reprogrammable
d) User-programmable, one-time programmable

Answer: d [Reason:] The fusible-link PROM is user programmable and one time programmable. It means that a written program can not be reprogrammed.

8. How can ultraviolet erasable PROMs be recognized?
a) There is a small window on the chip
b) They will have a small violet dot next to the #1 pin
c) Their part number always starts with a “U”, such as in U12
d) They are not readily identifiable, since they must always be kept under a small cover

Answer: a [Reason:] An ultraviolet erasable PROMs have small window on the chip with black marked.

9. Which part of a Flash memory architecture manages all chip functions?
a) Program verify code
b) Floating-gate MOSFET
c) Command code
d) Input/Output pins

Answer: b [Reason:] MOSFET technology is the best one in manufacturing of chip because it has high flexibility and storage capacity.

10. How much locations an 8-bit address code can select in memory?
a) 8 locations
b) 256 locations
c) 65,536 locations
d) 131,072 locations

Answer: b [Reason:] An 8 bit address code requires 32 memory locations and it can hold maximum upto 32 * 8 = 256 locations.

11. What is a fusing process?
a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) None of the Mentioned

Answer: c [Reason:] Fusing is a process by which programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

12. Fusing process is
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous

Answer: b [Reason:] Since, any program can not be reprogrammed in a PROM, so this process is irreversible.

13. The cell type used inside a PROM is
b) Metal cells
c) Fuse cells
d) Electric cells

Answer: c [Reason:] The cell type used inside a PROM is fuse cells by which a program is burnout.

14. How many types of fuse technologies are used in PROMs?
a) 2
b) 3
c) 4
d) 5

Answer: b [Reason:] Three type of fuse technologies are used in PROMs and these are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.

a) Polycrystalline
b) Magnesium sulphide
c) Nichrome
d) Silicon dioxide

## Set 4

1. What is access time?
a) The time taken to move a stored word from one bit to other bit after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits

Answer: c [Reason:] The access time is the time taken to read a stored word after applying the address bits in a MOS EPROM.

2. What are the typical values of tOE?
a) 10 to 20 ns for bipolar
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS
d) All of the Mentioned

Answer: d [Reason:] The typical values of tOE (i.e. access time) are mentioned above.

3. Which of the following is not a type of memory?
a) RAM
b) FPROM
c) EEPROM
d) ROM

Answer: c [Reason:] EEPROM (Electrical Erasable Programmable ROM) is not a type of memory because it is used for erasing purpose only.

4. The chip by which both the operation of read and write is performed
a) RAM
b) ROM
c) PROM
d) EPROM

Answer: a [Reason:] A Random Access Memory (RAM) is a volatile chip memory in which both the read and write operations can be performed.

5. RAM is also known as
a) RWM
b) MBR
c) MAR
d) None of the Mentioned

Answer: a [Reason:] RAM is also known as RWM (i.e. Read Write Memory).

6. If a RAM chip has n address input lines then it can access memory locations upto
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n

Answer: c [Reason:] If a RAM chip has n address input lines then it can access memory locations upto 2^n.

7. The n-bit address is placed in the
a) MBR
b) MAR
c) RAM
d) ROM

Answer: b [Reason:] The n-bit address is placed in the Memory Address Register (MAR) to select one of 2^n memory locations.

8. Which of the following control signals are selected for read and write operations in a RAM.
a) Data buffer
b) Chip select
d) None of the Mentioned

Answer: c [Reason:] Read and write are control signals that are used to enable memory for read and write operations respectively.

9. Computers invariably use RAM for
a) High complexity
b) High resolution
c) High speed main memory
d) High flexibility

Answer: c [Reason:] Computers invariably use RAM for their high high-speed main memory and then use backup or slower-speed memories to hold auxiliary data.

10. How many types of RAMs are?
a) 2
b) 3
c) 4
d) 5

Answer: a [Reason:] There are two types of RAM and these are static and dynamic.

11. Static RAM employs
a) BJT or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS

Answer: d [Reason:] Static RAM employs bipolar or MOS flip-flops because both the semiconductor has storing capacity.

12. Dynamic RAM employs
a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS

Answer: a [Reason:] Dynamic RAM employs capacitor or MOSFET.

13. Which one of the following is volatile in nature?
a) ROM
b) EROM
c) PROM
d) RAM

Answer: d [Reason:] RAMs are volatile because the stored data will be lost once the d.c. power applied to the flip-flops is removed.

14. The magnetic core memories have been replaced by semiconductor RAMs, why?
a) Semiconductor RAMs are highly flexible
b) Semiconductor RAMs has highest storing capacity
c) Semiconductor RAMs are smaller in size
d) All of the Mentioned

Answer: d [Reason:] The magnetic core memories have been replaced by semiconductor RAMs because of smaller in size, high storing capacity as well as flexibility.

15. The data written in flip-flop remains stored as long as
a) D.C. power is supplied
b) D.C. power is removed
c) A.C. power is supplied
d) A.C. power is removed

Answer: a [Reason:] Since, flip-flops are made up of semiconductor materials. So, it can’t accept A.C. source and the data written in flip-flop remains stored as long as the dc power is maintained.

## Set 5

1. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM

Answer: b [Reason:] ROM (Read Only Memory) has the capability to store the information permanently.

2. ROM has the capability to perform
a) Write operation only
c) Both write and read operation
d) Erase operation

Answer: b [Reason:] ROM means “Read Only Memory”. Hence, it has capability to perform read operation only.

3. Since, ROM has the capability to read the information only then also it has been designed, why?
a) For controlling purpose
c) For booting purpose
d) For erasing purpose

Answer: c [Reason:] It has designed to provide the computer with resident programmes and for booting purpose.

4. The ROM is a
a) Sequential circuit
b) Combinational circuit
c) Magnetic circuit
d) Static circuit

Answer: b [Reason:] ROM is a combination of different ICs. So, it is a combinational circuit.

5. ROM is made up of
a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
d) NAND and decoder

Answer: c [Reason:] ROM is made up of decoder and OR gates within a single IC package.

6. Why are ROMs called non-volatile memory?
a) They lose memory when power is removed
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied

Answer: b [Reason:] ROMs are called non-volatile memory because of they do not lose memory when power is removed.

7. In ROM, each bit is a combination of the address variables is called
a) Memory unit
b) Storage class
c) Data word

Answer: d [Reason:] In ROM, each bit is a combination of the address variables is called address.

8. Which is not a removable drive?
a) Zip
b) Hard disk
c) Super Disk
d) Jaz

Answer: c [Reason:] Hard disk is present inside a computer. So, it is not a removable drive.

9. In ROM, each bit combination that comes out of the output lines is called
a) Memory unit
b) Storage class
c) Data word