Digital Electronic MCQ Set 1
1. What is ambiguous condition in a NAND based S’-R’ latch?
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
Answer
Answer: d [Reason:] In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’) goes HIGH and this condition is called as ambiguous/forbidden state.
2. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is:
a) No change
b) Set
c) Reset
d) Forbidden
Answer
Answer: a [Reason:] In a NAND based S’-R, latch, if S’=1 & R’=1 then there is no any change in the state. It remains in its prior state.
3. A NAND based S’-R’ latch can be converted into S-R latch by placing
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
Answer
Answer: d [Reason:] A NAND based S’-R’ latch can be converted into S-R latch by placing either a D latch or an inverter at its input.
4. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) None of the Mentioned
Answer
Answer: a [Reason:] Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0 but 1 for NAND latch.
5. The characteristic equation of S-R latch is
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
Answer
Answer: a [Reason:] The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R’.
6. The difference between a flip-flop & latch is
a) Both are same
b) Flip-flop consist of an extra output
c) Latches has two inputs but flip-flop has two
d) None of the Mentioned
Answer
Answer: c [Reason:] Flip-flop is a modified version of latch. To determine the changes in states, an additional control input is provided to the latch.
7. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
Answer
Answer: c [Reason:] There are 4 types of flip-flops, viz., S-R, J-K, D, and T.
8. The S-R flip flop consist of
a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) None of the Mentioned
Answer
Answer: b [Reason:] The S-R flip flop consist of two additional AND gates at the S and R inputs of S-R latch.
9. What is one disadvantage of an S-R flip-flop?
a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) None of the Mentioned
Answer
Answer: d [Reason:] The main drawback of s-r flip flop is invalid output when both the inputs are high, which is not mentioned in the options.
10. One example of the use of an S-R flip-flop is as:
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
Answer
Answer: c [Reason:] S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as binary storage element.
11. When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) None of the Mentioned
Answer
Answer: b [Reason:] Flip-flop have the property of responding immediately to the changes in its inputs. This property is called transparency.
12. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Answer
Answer: c [Reason:] Edge triggered device will follow when there is transition. And positive edge triggered when transition takes place from low to high.
13. What is the hold condition of a flip-flop?
a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
Answer
Answer: b [Reason:] The hold condition in a flip-flop is obtained when both of the inputs are LOW.
14. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid
Answer
Answer: b [Reason:] If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in reset.
15. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
Answer
Answer: a [Reason:] The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the edge-detection circuit.
Digital Electronic MCQ Set 2
1. The memory capacity of a static RAM varies from
a) 32 bit to 64 bit
b) 64 bit to 1024 bit
c) 64 bit to 1 Mega bit
d) 512 bit to 1 Mega bit
Answer
Answer: c [Reason:] The memory capacity of a static RAM varies from 64 bits to 1 Mega bit.
2. The input data bit is written into the cell by setting
a) The flip-flop for 1
b) Resetting the flip-flop
c) The flip-flop for HIGH
d) Both the flip-flop for 1 and resetting the flip-flop
Answer
Answer: d [Reason:] The input data bit (1 or 0) is written into the cell by setting the flip-flop for 1 and the resetting the flip-flop for a 0 when the R/W’ line is low.
3. When the READ/(WRITE)’ line is HIGH then the flip-flop is
a) Activated
b) Deactivated
c) Unaffected
d) Both activated and deactivated
Answer
Answer: c [Reason:] When the READ/(WRITE)’ line is HIGH then the flip-flop is unaffected. It means that the stored bit (data) is gated to the data out line.
4. The flip-flop in static memory cell can be constructed using
a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOSFET
Answer
Answer: d [Reason:] The flip-flop in static memory cell can be constructed using Bipolar Junction Transistor (BJT) and MOSFETs.
5. Which of the following IC is TTL based static RAM?
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
Answer
Answer: b [Reason:] In IC 7489, TTL is used which is static RAM.
6. IC 7489 is of
a) 32 bit
b) 64 bit
c) 512 bit
d) 1024 bit
Answer
Answer: b [Reason:] The arrangement of IC 7489 is 16 * 4 = 64 bits.
7. Data is written in IC 7489 through
a) Chip select
b) Enable
c) Data input
d) Memory enable
Answer
Answer: c [Reason:] Data can be written into the memory via the data inputs by supplying an address to the SELECT inputs and holding both the memory enable and write enable LOW.
8. The first practical form of Random Access Memory (RAM) was the
a) Cathode tube
b) Data tube
c) Memory tube
d) Select tube
Answer
Answer: c [Reason:] The first practical form of Random Access Memory (RAM) was the Williams tube starting in 1947. It stored data as electrically charged spots on the face of a cathode ray tube.
9. Magnetic-core memory was invented in
a) 1946
b) 1948
c) 1947
d) 1945
Answer
Answer: c [Reason:] Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings.
10. Which of the following RAM is volatile in nature?
a) SRAM
b) DRAM
c) EEPROM
d) Both SRAM and DRAM
Answer
Answer: d [Reason:] Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system.
11. Which one of the following IC is of 4KB?
a) IC 7488
b) IC 7489
c) IC 7487
d) IC 2114
Answer
Answer: d [Reason:] IC 2114 is of 4KB and it is a static RAM.
12. Which of the following IC implements the static MOS RAM?
a) TMS 4015
b) TMS 4014
c) TMS 4016
d) TMS 2114
Answer
Answer: c [Reason:] The IC TMS 4016 is a 2KB static MOS RAM.
13. What types of arrangements a TMS 4016 has?
a) 1024 * 4
b) 1024 * 8
c) 2048 * 4
d) 2048 * 8
Answer
Answer: d [Reason:] 2048 * 8 = 2KB.
14. How many address inputs are available in TMS 4016?
a) 10
b) 9
c) 12
d) 11
Answer
Answer: d [Reason:] There are eleven address inputs available to select the 2014 locations.
15. In TMS 4016, the data in/data out are
a) Unidirectional
b) Parallel
c) Serial
d) Bidirectional
Answer
Answer: d [Reason:] In TMS 4016, the data in/data out are bidirectional terminal. It means that the input/output can be given/received from both the sides.
Digital Electronic MCQ Set 3
1. Dynamic RAM is more preferable than static RAM, why?
a) DRAM is of the lowest cost, lowest density
b) DRAM is of the highest cost, reduced size
c) DRAM is of the lowest cost, highest density
d) DRAM is more flexible and lowest storage capacity
Answer
Answer: c [Reason:] The Dynamic Random Access Memory is the lowest cost, highest density random access memory available. Nowadays, computers use DRAM for main memory.
2. The memory size of DRAM is
a) 1 to 100 MB
b) 512 to 1024 MB
c) 64 to 512 MB
d) 16 to 256 MB
Answer
Answer: d [Reason:] The memory size of DRAM lies between 16 to 256 MB.
3. The DRAM stores its binary information on
a) MOSFET
b) Transistor
c) Capacitor
d) BJT
Answer
Answer: c [Reason:] Capacitor has high storing capability only, so DRAM stores its binary information in the form of electric charges on capacitors.
4. Most modern operating systems employ a method of extending RAM capacity, known as
a) Magnetic memory
b) Virtual memory
c) Storage memory
d) Static memory
Answer
Answer: b [Reason:] Most modern operating systems employ a method of extending RAM capacity, known as virtual memory.
5. DRAM uses of an integrated MOS capacitors as _______ instead of a flip-flop.
a) Storage cell
b) Memory cell
c) Dynamic cell
d) Static cell
Answer
Answer: b [Reason:] DRAM uses of an integrated MOS capacitors as memory cell instead of a flip-flop. The advantage of this cell is that it allows very large memory arrays to be constructed on a chip at a lower cost per bit than in static memories.
6. What is the disadvantage of MOS capacitor in DRAM?
a) It can’t hold the data till a long period
b) It doesn’t holds the charge till a long period
c) It is highly densed
d) It is not flexible
Answer
Answer: b [Reason:] The disadvantage of MOS capacitor in DRAM is that it can’t hold the stored charge over a long period of time and it has to be refreshed every few millisecond.
7. The dynamic RAM offers
a) High power consumption, large storage capacity
b) Reduced power consumption, large storage capacity
c) Reduced power consumption, short storage capacity
d) High power consumption, short storage capacity
Answer
Answer: b [Reason:] The dynamic RAM offers reduced power consumption and large storage capacity in a single memory chip. With the availability of such high packing density memory ICs, the capacity of memory will continue to grow.
8. The main memory of a PC is made of
a) Cache
b) Dynamic RAM
c) Static RAM
d) Both cache and dynamic RAM
Answer
Answer: d [Reason:] The main memory of a PC is made of cache and DRAM.
9. Virtual memory consist of
a) SRAM
b) DRAM
c) Magnetic memory
d) None of the Mentioned
Answer
Answer: a [Reason:] Most modern operating systems employ a method of extending RAM capacity, known as virtual memory which consist of SRAM.
10. Dynamic RAM is used as main memory in a computer system as
a) It has lower cell density
b) It needs refreshing circuitry
c) Consumes less power
d) has higher speed
Answer
Answer: d [Reason:] Dynamic RAM is used as main memory in a computer system as it has higher speed due to the presence of MOSFET technology.
11. Cache memory acts between
a) RAM and ROM
b) CPU and RAM
c) CPU and Hard Disk
d) None of the Mentioned
Answer
Answer: b [Reason:] In a computer, cache memory acts between CPU and RAM.
12. Which characteristic of RAM memory makes it not suitable for permanent storage?
a) Unreliable
b) Too slow
c) Too bulky
d) It is volatile
Answer
Answer: d [Reason:] RAM is volatile.
13. Why do a DRAM employ address multiplexing technique?
a) To reduce the number of memory locations
b) To increase the number of memory locations
c) To reduce the number of address lines
d) None of the Mentioned
Answer
Answer: c [Reason:] A Dynamic RAM usually employs a technique called address multiplexing to reduce number of address lines and thus the number of the number of input/output pins on the IC package.
14. An address multiplexing in DRAM is of _____ bits.
a) 10240
b) 15289
c) 16384
d) 17654
Answer
Answer: c [Reason:] Address multiplexing has 2^14 = 16384 bits.
15. What is a sense amplifier?
a) It is an amplifier which converts ac current into dc current
b) It is an amplifier which lowers the input voltage
c) It is an amplifier which increases the input voltage
d) It is an amplifier which converts the low voltage to a sufficient voltage
Answer
Answer: d [Reason:] A sense amplifier for each column is necessary to convert from the low voltage and low energy to a sufficient level on the I/O data line.
Digital Electronic MCQ Set 4
1. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) None of the Mentioned
Answer
Answer: a [Reason:] For one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.
2. Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer
Answer: b [Reason:] Demultiplexer converts single input into multiple outputs.
3. In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5
Answer
Answer: a [Reason:] The formula for total no. of outputs is given by: 2^n, where n is the no. of select lines.
4. In a multiplexer the output depends on its
a) Data inputs
b) Select inputs
c) Select outputs
d) None of the Mentioned
Answer
Answer: b [Reason:] As the select input changes, the output of the multiplexer varies according to that input.
5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be
a) Y0
b) Y1
c) Y2
d) Y3
Answer
Answer: d [Reason:] The output y3 = C1.C0.X.
6. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer
Answer: b [Reason:] The formula for total no. of outputs is given by: 2^n, where n is the no. of select lines. In this case n = 3.
7. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 4
d) 5
Answer
Answer: c [Reason:] The number of AND gates required will be equal to the number of outputs in a demultiplexer.
8. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer
Answer: a [Reason:] IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.
Digital Electronic MCQ Set 5
1. The output of an EX-NOR gate is 1. Which input combination is correct?
a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) None of the Mentioned
Answer
Answer: c [Reason:] The output of EX-NOR gate is given by (AB’ + A’B)’. So, for A = 0 and B = 0 the output will be 1.
2. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR
Answer
Answer: d [Reason:] In or gate we need at least one bit to be equal to 1 to generate the output as 1 because OR means any of the condition out of two is equal to 1 which means if at least one input is 1 then it shows output as 1.
3. The time required for a gate or inverter to change its state is called
a) Rise time
b) Decay time
c) Propagation time
d) Charging time
Answer
Answer: c [Reason:] The time required for a gate or inverter to change its state is called propagation time.
4. What is the minimum number of two input NAND gates used to perform the function of two input OR gates?
a) One
b) Two
c) Three
d) Four
Answer
Answer: c [Reason:] Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create OR gate. We can also write,
1st, 2nd and 3rd NAND operations as: Y = (A AND B)’ = A.B = (A.B)’.
5. Odd parity of word can be conveniently tested by
a) OR gate
b) AND gate
c) NAND gate
d) XOR gate
Answer
Answer: d [Reason:] Odd parity of word can be conveniently tested by XOR gate.
6. The number of full and half adders are required to add 16-bit number is
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
Answer
Answer: b [Reason:] One half adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15 bits as they all involve adding carries.
7. Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter
Answer
Answer: d [Reason:] Three bit counter will give the sum of full adders as output.
8. Which of the following gate is known as coincidence detector?
a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
Answer
Answer: a [Reason:] AND gate is known as coincidence detector due to multiplicity behaviour.
9. An OR gate can be imagined as
a) Switches connected in series
b) Switches connected in parallel
c) MOS transistor connected in series
d) None of the mentioned
Answer
Answer: b [Reason:] OR gate means addition of two inputs, due to this reason it is imagined as switches connected in parallel.
10. How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1
Answer
Answer: c [Reason:] We need adder for every bit. So we should need m bit adders. A full adder adds a carry bit to two inputs and produces an output and a carry. But the most significant bits can use a half adder which differs from the full adder as in that it has no carry input, so we need m-1 full adders in m bit parallel adder.
