Digital Electronic MCQ Set 1
1. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Answer
Answer: c [Reason:] A transistor can be used as a switch. That is, when base is low collector is high (input zero, output one) and base is high collector is low (input 1, output 0).
2. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
Answer
Answer: d [Reason:] For 2 inputs: 2^2 = 4 truth table entries are necessary.
3. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
Answer
Answer: c [Reason:] For AND gate, the output is high only when both inputs are high. That’s why the high output in AND will occurs only when all the inputs are high.
4. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
Answer
Answer: c [Reason:] Expression for XOR is: A.(B’)+(A’).B
so in the above expression the following logic gates are used: AND, OR, NOR.
5. The basic logic gate whose output is the complement of the input is the:
a) OR gate
b) AND gate
c) INVERTER gate
d) Comparator
Answer
Answer: c [Reason:] It is also called NOT gate and it simply inverts the input.
6. The AND function can be used to _____ and the OR function can be used to _______
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
Answer
Answer: a [Reason:] Because of their multiplicity and additivity property respectively.
7. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
Answer
Answer: a [Reason:] The dependency notation “>=1” inside a block stands for OR operation.
8. If we use an AND gate to inhibit a signal from passing one of the inputs must be
a) LOW
b) HIGH
c) Inverted
d) Floating
Answer
Answer: a [Reason:] AND gate means A*B and OR gate means A+B and to inhibit means to get low signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal.
9. Logic gate circuits contain predictable gate functions that open theirs
a) Outputs
b) Inputs
c) Pre-state
d) None of the Mentioned
Answer
Answer: b [Reason:] Logic gate circuits contain predictable gate functions that open their inputs because we are free to give any types of inputs.
10. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
Answer
Answer: c [Reason:] 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc and remaining pins used for connections. For a NAND gate two inputs are required and one output is obtained means for NAND gate 3 pin connections are required.
Digital Electronic MCQ Set 2
1. When two or more devices try to write data in a bus simultaneously, is known as
a) Bus collisions
b) Address multiplexing
c) Address decoding
d) Bus contention
Answer
Answer: d [Reason:] Bus contention is an undesirable state of the bus of a computer, in which more than one memory mapped device, or the CPU is attempting to place output values onto the bus at once.
2. A memory is a collection of
a) Unit cells
b) Storage cells
c) Data cells
d) None of the Mentioned
Answer
Answer: b [Reason:] A memory is a collection of storage cells with associated circuits needed to transfer information.
3. To transfer the information from input to output and vice versa, the cells used is
a) Storage cells
b) Data cells
c) Unit cells
d) Both data and unit cells
Answer
Answer: a [Reason:] To transfer the information from input to output and vice versa, the cells used is called storage cells.
4. The data stored in group of bits is called
a) Nibble
b) Word
c) Byte
d) Address
Answer
Answer: b [Reason:] The data stored in group of bits is called word.
5. Each word consist of a sequence of
a) Letters
b) Binary numbers
c) Hexadecimal numbers
d) Gray codes
Answer
Answer: b [Reason:] Each word consist of a sequence of 0s and 1s (i.e. binary numbers).
6. Each word stored in a memory location is represented by
a) RAM
b) ROM
c) Storage class
d) Address
Answer
Answer: d [Reason:] Each word stored in a memory location is represented by address.
7. The group of each 8-bit is called
a) Nibble
b) Flag
c) Byte
d) Word
Answer
Answer: c [Reason:] 1 byte = 8-bit.
8. The capacity of a memory unit is
a) The number of binary input stored
b) The number of words stored
c) The number of bytes stored
d) All of the Mentioned
Answer
Answer: c [Reason:] The total number of bytes that can be stored, is the maximum capacity of a memory unit.
9. The communication between a memory and its environment is achieved through
a) Control lines
b) Data input/output lines
c) Address selection lines
d) All of the Mentioned
Answer
Answer: d [Reason:] Firstly, the data input is needed to transfer the information and it is passed through the address lines and then controlled by control lines.
10. One of the most important specifications on magnetic media is the
a) Polarity reversal rate
b) Tracks per inch
c) Data transfer rate
d) Rotation speed
Answer
Answer: c [Reason:] The rate of data transfer depends on the properties of magnetic media.
Digital Electronic MCQ Set 3
1. To realise one flip-flop using another flip-flop along with a combinational circuit, known as
a) PREVIOUS state decoder
b) NEXT state decoder
c) MIDDLE state decoder
d) None of the Mentioned
Answer
Answer: b [Reason:] To realise one flip-flop using another flip-flop along with a combinational circuit, known as NEXT state decoder which acts as like a flip-flop.
2. For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as
a) External inputs to S and R
b) Internal inputs to S and R
c) External inputs to combinational circuit
d) Internal inputs to combinational circuit
Answer
Answer: a [Reason:] If a JK Flip Flop is required, the inputs are given to the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip flop. So, J and K will be given as external inputs to S and R.
3. For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
Answer
Answer: b [Reason:] If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND gates which results as S=0 & R=X(i.e. don’t care).
4. For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then excitation input will be
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
Answer
Answer: c [Reason:] If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which results excitation inputs as S=1 & R=0.
5. For realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from
a) S and R
b) R input
c) J and K input
d) None of the Mentioned
Answer
Answer: c [Reason:] It is the reverse process of SR flip-flop to JK flip-flop. So, for realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from J and K.
6. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then next state will be
a) 1
b) 0
c) Don’t care
d) Toggle
Answer
Answer: a [Reason:] For JK flip-flop to SR flip-flop, if S=1, R=0 & present state is 0 then next state will be 0 because next stage is complement of present stage.
7. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
Answer
Answer: c [Reason:] For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the excitation input will be J=1, K=X.
8. The K-map simplification for realisation of SR flip-flop from JK flip-flop is
a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) None of the Mentioned
Answer
Answer: c [Reason:] The K-map simplification for realisation of SR flip-flop from JK flip-flop is given by: J=S, K=R.
9. For realisation of D flip-flop from SR flip-flop, the external input is given through
a) S
b) R
c) D
d) Both S and R
Answer
Answer: c [Reason:] For realisation of D flip-flop from SR flip-flop, S and R are the actual inputs of the flip flop which is connected together via NOT gate and it is called external input as D.
10. For D flip-flop to JK flip-flop, the characteristics equation is given by:
a) D=JQ(p)’+Q(p)K’
b) D=JQ(p)’+KQ(p)’
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
Answer
Answer: a [Reason:] For D flip-flop to JK flip-flop, the characteristics equation is given by D=JQ(p)’+Q(p)K’.
Digital Electronic MCQ Set 4
1. SSI refers to
a) Small Scale Integration
B) Short Scale Integration
c) Small Set Integration
d) None of the Mentioned
Answer
Answer: a [Reason:] SSI refers to Small Scale Integration.
2. Small Scale Integration(SSI) refers to ICs with ____ gates on the same chip.
a) Fewer than 10
b) Greater than 10
c) Equal to 10
d) None of the Mentioned
Answer
Answer: a [Reason:] Small Scale Integration(SSI) refers to ICs with fewer than 10 gates on the same chip.
3. MSI means
a) Merged Scale Integration
b) Main Scale Integration
c) Medium Scale Integration
d) None of the Mentioned
Answer
Answer: c [Reason:] MSI means Medium Scale Integration.
4. MSI includes _______ gates per chip.
a) 12 to 100
b) 13 to 50
c) greater than 10
d) None of the Mentioned
Answer
Answer: a [Reason:] Medium Scale Integration includes 12 to 100 gates per chip.
5. LSI means ________ and refers to ________ gates per chip.
a) Long Scale Integration, more than 10 upto 10000
b) Large Scale Integration, more than 100 upto 5000
c) Large Short Integration, less than 10 and greater than 5000
d) None of the Mentioned
Answer
Answer: b [Reason:] The full form of LSI is Large Scale Integration and refers to more than 100 upto 5000 gates per chip.
6. Integrated circuits are classified as
a) Large, Small and Medium
b) Very Large, Small and Linear
c) Linear and Digital
d) None of the Mentioned
Answer
Answer: c [Reason:] Integrated circuits are classified as Linear and Digital. Linear operates with continuous and digital refers to discrete signals.
7. According to the IC fabrication process logic families can be divided into two broad categories as:
a) RTL and TTL
b) HTL and MOS
c) ECL and DTL
d) Bipolar and MOS
Answer
Answer: d [Reason:] According to the IC fabrication process logic families can be divided into two broad categories as: Bipolar and Metal-oxide semiconductor. The mentioned all others are part of bipolar.
8. The full form of DIP is
a) Dual-in-Long Package
b) Dual-in-Line Package
c) Double Integrated Package
d) Double-in-Line Package
Answer
Answer: b [Reason:] The full form of DIP is Dual-in-Line Package.
9. LCC refers to
a) Longest Chip Carrier
b) Leadless Chip Carrier
c) Leaded Chip Carrier
d) None of the Mentioned
Answer
Answer: b [Reason:] LCC refers to Leadless Chip Carrier.
10. PGA refers to
a) Plastic Grid Array
b) Pin Grid Array
c) Pin Greater Array
d) None of the Mentioned
Answer
Answer: b [Reason:] PGA refers to Pin Grid Array.
Digital Electronic MCQ Set 5
1. Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
Answer
Answer: d [Reason:] Since, both inputs of the D flip-flop are connected through an inverter. And this causes reduction in the number of inputs.
2. The characteristic of J-K flip-flop is similar to
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) None of the Mentioned
Answer
Answer: a [Reason:] In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same behaviour is shown by J-K flip-flop.
3. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) None of the Mentioned
Answer
Answer: a [Reason:] A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.
4. How is a J-K flip-flop made to toggle?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer
Answer: d [Reason:] When j=k=1 then the race condition is occurs that means both output wants to be HIGH. Hence, there is toggle condition is occurs.
5. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital filtering
Answer
Answer: b [Reason:] Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.
6. In J-K flip-flop, “no change” condition appears when
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
Answer
Answer: d [Reason:] If J = 0, K = 0, the output remains unchanged.
7. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
Answer
Answer: d [Reason:] The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.
8. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use
Answer
Answer: c [Reason:] The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit.
9. On a J-K flip-flop, when is the flip-flop in a hold condition?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer
Answer: a [Reason:] At J=0 k=0 output continues to be in the same state.
10. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10
Answer
Answer: a [Reason:] Every O/P repeats after its mod here mod is 4 so after 4 clock pulses the O/P repeats i.e. 00.
11. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
Answer
Answer: b [Reason:] 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-flop.
12. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
Answer
Answer: b [Reason:] 12 flip flops = 2^12 = 4096
=> 20.48*10^6 = 20480000
=> 20480000/4096 = 5000 i.e., 5 kHz.
13. How many flip-flops are in the 7475 IC?
a) 2
b) 1
c) 4
d) 8
Answer
Answer: c [Reason:] There are4 flip-flops used in 7475 IC and these are RS flip-flop, JK flip-flop, D flip-flop, T flip-flop.
