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1. MSP430 uses vectored interrupts?
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] MSP430 has vectored interrupts i.e. the address of each ISR is stored in a vector table, that’s why it has vectored interrupts.

2. Which of the following is true?
a) interrupts are required to wake a CPU from sleep
b) more then one interrupt can share a same vector address
c) most interrupts are mask able
d) all of the mentioned

View Answer

Answer: d [Reason:] All of the above mentioned statements are true i.e. interrupts are required to wake a CPU from sleep, more than one interrupt can share a same vector address and most of the interrupts are maskable.

3. After interrupt has occurred, the stack is filled with
a) return address
b) status register
c) both of the mentioned
d) none of the mentioned

View Answer

Answer: c [Reason:] When an interrupt had occurred, the top place of the stack is filled with the return address, so that immediately after the reti instruction the pointer moves to the main program, the stack is also filled with the bits of the status register so that all the temporary values get stored in it.

4. What is the function of __ __interrupt keyword
a) it is used to enable the interrupt
b) it is used to disable the interrupt
c) it is used to assign a particular address to a vector
d) all of the mentioned

View Answer

Answer: c [Reason:] __ __interrupt keyword is used to assign a particular address to a vector. It just acts as a function that tells us about the beginning of the line.

5. What is the difference between the INTVEC and the RSEG keywords?
a) so that more than one file can store the interrupt vectors in the segment
b) one is used for storage, other for display
c) one stores locally other stores globally
d) the two are the same

View Answer

Answer: a [Reason:] INTVEC is used so that more than one file can store the interrupt vectors in the segment.

6. For enabling any interrupt, firstly
a) GIE=0
b) GIE=1
c) None of the mentioned
d) Both of the mentioned

View Answer

Answer: b [Reason:] If GIE is set to 1, then only other hardware interrupts are enabled.

7. Non mask able vectors are stored at different vector locations?
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] Non mask able interrupts are stored in the same vector location, it may be of higher or the lower priority.

8. Which of the following can generate a non mask able interrupt?
a) access violation to flash memory, ACCVIFG
b) timer_A interrupt
c) compare / capture interrupt
d) all of the mentioned

View Answer

Answer: a [Reason:] A non mask able interrupt is generated by a access violation to flash memory, ACCVIFG.

9. External RST/NMI pin is a non maskable interrupt?
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] Yes, external RST/NMI pin is a non maskable interrupt( The function of the RST/NMI pin is configured in the control register for the watchdog timer module, WDTCTL).

10. How many cycles are used by MSP430, when reti instruction is executed?
a) 3
b) 4
c) 5
d) depends on the conditions

View Answer

Answer: c [Reason:] When reti instruction is executed, five cycles are used because it firstly pops the stack register completely and then takes the top of the stack into the PC to return to the next address of the main program.

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