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Online MCQ Assignment
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1. On reset, what are the contents of the SREG register?
a) 00h
b) ffh
c) 1fh
d) 11h

View Answer

Answer: a [Reason:] On reset, all the interrupts are masked and so the contents of the SREG register is also set to zero as it shows the status of the flags.

2. TIMSK register is used for?
a) knowing the status of the timer count
b) used for masking the interrupts flags of the Timer0, Timer1 and Timer2
c) it is used for enabling all the timer interrupts
d) it is used for resetting the value of the interrupts

View Answer

Answer: b [Reason:] TIMSK is used for masking the interrupt flags of the timers. They mask the bits of the timer flags if the D7 bit of the SREG register is set to 1 or when firstly all interrupts are enabled.

3. Why RETI instruction is used after an ISR?
a) because it returns with carry
b) because it returns to the main program with all the flags of the SREG raised
c) because it returns to the main program after clearing the roll over flag of the interrupt, so that the interrupt can be caused again
d) none of the mentioned

View Answer

Answer: c [Reason:] RETI instruction is used to make the timer roll over flag to zero, so that the interrupt may be caused again.

4. In AVR what is the ISR address for an external hardware interrupt?
a) 0002h
b) 0004h
c) 0006h
d) all of the mentioned

View Answer

Answer: d [Reason:] The ISR addresses for the external hardware interrupts are 0002h, 0004h, 0006h.

5. What is the address in the interrupt service routine assigned for the timer0 overflow flag?
a) 0012h
b) 000Ah
c) 0016h
d) all of the mentioned

View Answer

Answer: c [Reason:] 0016h is the address in the interrupt service routine assigned for the timer0 overflow flag.

6. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of the interrupts?
a) true
b) false
c) can’t be determined
d) depends on the situation

View Answer

Answer: b [Reason:] Different addresses are assigned for Timer0 and Timer1 overflow flags in the interrupt vector table. They are 0016h and 0012h for timer0 and timer1 respectively.

7. External hardware interrupts are assigned to which pins of the atmega32?
a) PORTD.2
b) PORTD.3
c) All of the mentioned
d) None of the mentioned

View Answer

Answer: d [Reason:] Their are three external hardware interrupts in the atmega32 micro controllers. They are assigned to bits PORTD.2, PORTD.3 and PORTB.2.

8. Which register is responsible for handling all the external hardware interrupts?
a) TIMSK
b) GICR
c) MCUCR
d) IVCE

View Answer

Answer: b [Reason:] GICR register is responsible for all the external hardware interrupts in the AVR.

9. By default, INT0-INT2 interrupts are?
a) edge triggered
b) level triggered
c) all of the mentioned
d) none of the mentioned

View Answer

Answer: b [Reason:] By default, INT0-INT2 are the level triggered pulses. The low level of the pulse generates the interrupt.

10. What will happen in that condition, if an interrupt occurs while the micro controller is serving any other interrupt?
a) both the interrupts will be handled simultaneously
b) the interrupt which is being done first will be served first
c) the interrupt that is more priority in the interrupt vector table will be served first
d) the interrupt having low priority in the interrupt vector table will be served first

View Answer

Answer: c [Reason:] If two or more interrupts, occur simultaneously then the interrupt that is having more priority in the interrupt vector table will be served first.

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