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## Linear Integrated MCQ Set 1

1. Open loop op-amp configuration has
a) Direct network between output and input terminals
b) No connection between output and feedback network
c) No connection between input and feedback network
d) All of the mentioned

Answer: a [Reason:] In an open loop configuration, the output signal is not fed back in any form as part of the input signal and the loop that would have been formed with feedback is open.

2. In which configuration does the op-amp function as a high gain amplifier?
a) Differential amplifier
b) Inverting amplifier
c) Non-inverting amplifier
d) All of the mentioned

Answer: d [Reason:] An op-amp functions as a high gain amplifier when connected in open loop configuration. These three are the open loop configuration of an op-amp.

3. How does the open loop op-amp configuration classified?
a) Based on the output obtained
b) Based on the input applied
c) Based on the amplification
d) Based on the feedback network

Answer: b [Reason:] Open loop configurations are classified according to the number of inputs used and the terminal to which the input is applied when a single input is used.

4. What will be the voltage drop across the source resistance of differential amplifier when connected in open loop configuration?
a) Zero
b) Infinity
c) One
d) Greater than one

Answer: a [Reason:] The source resistances are normally negligible compared to the input resistance. Therefore, the voltage drop across input resistors can be assumed to be zero.

5. The output voltage of an open-loop differential amplifier is equal to
a) Double the difference between the two input voltages
b) Product of voltage gain and individual input voltages
c) Product of voltage gain and the difference between the two input voltages
d) Double the voltage gain and the difference between two input voltages

Answer: c [Reason:] The output voltage is equal to the voltage gain times the difference between the two input voltages.

6. Calculate the output voltage for the given circuit. a) Vo = 7v
b) Vo = 5.9v
c) Vo = 12v
d) Vo = 11.4v

Answer: c [Reason:] The output voltage, Vo = A*(Vin1-Vin2).(Since, Rin1 and Rin2 are negligible compared to input resistance in open loop differential amplifier). => Vo = 4*(12v-9v) = 12v.

7. Find the output of inverting amplifier?
a) Vo = AVin
b) Vo = -AVin
c) Vo = -A(Vin1– Vin2)
d) None of the mentioned

Answer: b [Reason:] In an inverting amplifier the input signal is amplified by gain A and is also inverted at the output. The negative sign indicates that the output voltage is of opposite polarity.

8. Determine the output voltage for the non-inverting amplifier input voltage 37µVpp sinewave. Assume that the output is a 741.
a) -7.44 Vpp sinewave
b) 74 Vpp sinewave
c) 7.4Vpp sinewave
d) 0.7 Vpp sinewave

Answer: c [Reason:] The output voltage for non-inverting amplifier Vo = A*Vin = 200000 * 37µ = 7.4 Vpp sinewave.

9. Find the non-inverting amplifier configuration from the given circuit diagram? Answer: c [Reason:] In a non-inverting amplifier, the input is applied to the non-inverting input terminal and the inverting terminal is connected to ground.

10. What happen if any positive input signal is applied to open-loop configuration?
a) Output reaches saturation level
b) Output voltage swing’s peak to peak
c) Output will be a sine waveform
d) Output will be a non-sinusoidal waveform

Answer: a [Reason:] In open-loop configuration, due to very high gain of the op-amp, any input signal slightly greater than zero drives the output to saturation level.

11. Why open-loop op-amp configurations are not used in linear applications?
a) Output reaches positive saturation
b) Output reaches negative saturation
c) Output switches between positive and negative saturation
d) Output reaches both positive and negative saturation

Answer: c [Reason:] When operated in open loop, the output switches between positive and negative saturation levels. For this reason, open loop op-amp configurations are not used in linear applications.

## Linear Integrated MCQ Set 2

1. Determine the output voltage for an op-amp with single break frequency. a) VO ={ jXC /[Ro+(iXC)]} × AVid
b) VO = = AVid / [1+ j2πfRoC].
c) VO = AVid /(Ro+j2πfC)
d) VO = Vid / [Ro-(j2πfRoC)].

Answer: b [Reason:] The output voltage for an op-amp with single break frequency, VO = {(-jXC) / [(Ro)-(jXC)} ×AVid ∵ -j=1/j & XC =1/2πfC => VO = {(1/j2ΠfC)/[Ro + (1/ j2πfC)] } × AVid = AVid / [1+ j2πfRoC].

2. Compute the break frequency of an op-amp, if the output resistance=10kΩ and capacitor connected to the output =0.1µF.
a) 159.2Hz
b) 6.28Hz
c) 318.4Hz
d) 1000Hz

Answer: a [Reason:] Break frequency of the op-amp is given as fo = 1/(2πRoC)= 1/ (2π×10kΩ×0.1µF) = 1/ (6.28×10-3) = 159.2Hz.

3. The open loop voltage gain as a function of frequency is defined as
a) AOL(f) = VO/Vin
b) AOL(f) = VO/Vid
c) AOL(f) = VO/Vf
d) All of the mentioned

Answer: b [Reason:] The open loop voltage gain as a function of frequency is defined as ratio of output voltage to the difference of input voltages.

4. Which among the following factor remain fixed for an op-amp?
a) Open loop voltage gain
b) Gain of the op-amp
c) Operating frequency
d) Break frequency of the op-amp

Answer: d [Reason:] Break frequency fo depends on the value of capacitors and on output resistance. Therefore, fo is fixed for any op-amp.

5. Find the gain magnitude and phase angle of the op-amp using the specifications:
f= 50Hz; fo=5Hz ; A=140000.
a) AOL(f)= 22.92dB , Φ(f) = – 89.99o
b) AOL(f)= 66dB , Φ(f) = – 90o
c) AOL(f)= 26dB, Φ(f) = – 89.99o
d) AOL(f)= 20dB , Φ(f) = – 84.29o

Answer: a [Reason:] The open loop gain magnitude |AOL(f)|= 20log[A/√[1+ f/fo)2] = 20logA-20 log[A/√ [1+(f/fo)2] = 20log(140000)- 20log[√(1+(50,000/5)2)] AOL(f) dB= 102.922-80 = 22.92dB. Phase angle, φ(f) = -tan-1(f/fo) = -tan-1(50000/5) = -89.99o.

6. Consider an op-amp where the inverting input voltage =3.7mv, non-inverting input voltage=6.25mv and open loop voltage gain =142dB. Find the output voltage.
a) 0.21v
b) 0.45v
c) 0.78v
d) 0.36v

Answer: d [Reason:] Open loop voltage gain, AoL(f) = Vo/Vid VO = AOL(f) × (Vin1-Vin2) = 142 dB×(6.25-3.7) = 142×2.55 = 0.36v.

7. Express the open loop gain of the op-amp in complex form?
a) A/√ [1+(f/fo)2
b) 20log{A/√[1+(f/fo)2}
c) A/[1+j(f/fo)].
d) None of the mentioned

Answer: c [Reason:] The open loop gain of the op-amp AOL(f) is a complex quantity and is expressed as AOL(f) = A/[1+ j(f/fo)] . The remaining equations are expressed in polar form.

8. Determine the difference between two AOL(f) at 50Hz and 500Hz frequency? (Consider the op-amp to be 741c)
a) 40dB
b) 30dB
c) 20dB
d) 10dB

Answer: c [Reason:] AOL(f) dB= 20log[√ [1+ (f/fo)2] At f= 50 Hz, AOL(f) dB = 20log(200000)- 20log(√(1+(50/5)2) = 106.02-20.04 ≅ 86dB At f= 500Hz AOL(f) dB =20log(200000)-20log(√(1+(500/5)2) = 106.02-40 ≅ 66dB Therefore, the difference between AOL(f)dB = 86-66 = 20dB.

9. At what frequency, the phase shift between input &output voltage will be zero?
a) -40Hz
b) 0Hz
c) -22Hz
D) 20Hz

Answer: b [Reason:] At 0Hz the phase shift between input and output voltage is zero. At f=0Hz, φ(f) = – tan-1 (f/fo) = -tan-1(0/5) = 0o

10. At what frequency AOL(f)=A?
a) 50Hz
b) 10Hz
c) 5Hz
d) 0Hz

Answer: d [Reason:] For any frequency less than break frequency (fo =5Hz) the gain is approximately constant and is equal to A. For example, fo =0Hz, Then AOL(f) dB= 20log(200000-20log[√1+(0/5)2)] = 106dB. Where A =20,000 ≅ 106dB.

11. What happen when the frequency increases?
a) AOL(f) continues to drop
b) A increases
c) fo –> 0Hz
d) None of the mentioned

Answer: a [Reason:] The open loop voltage gain as a function of frequency is given as AOL(f) = A/ [√ 1+ (f/fo)] at frequency above fo, the denominator value increases, causing the gain, AOL(f) to decrease. Thus, as frequency increases, the gain AOL(f) continuous to drop.

12. What will be the absolute value of phase shift, if the frequency keeps increasing?
a) Increase towards 45o
b) Decrease towards 45o
c) Increase towards 90o
d) Decrease towards 90o

Answer: c [Reason:] For any frequency above break frequency, the absolute value of phase shift increases towards 90o with increase in frequency.

## Linear Integrated MCQ Set 3

1. Which circuit can be used as a full wave rectifier?
a) Absolute vale output circuit
b) Positive clipper with two diodes
c) Negative clipper with two diodes
d) Peak clampers

Answer: a [Reason:] Absolute value output circuit produces an output signal that swings positively only, regardless of the polarity of the input signal; because of the nature of its output wave form, the circuit is used as full wave rectifier.

2. For the circuit shown below find the output voltage a) Vo (+) = +10 v
b) Vo (+) = +12v
c) Vo (+) = +7v
d) None of the mentioned

Answer: b [Reason:] The voltage at the terminal V1 = (Vp -Vd1) /2 V1 = (12-0.7) /2 = 5.65 v (Vd1= voltage drop across diode=0.7) Similarly, the voltage at the negative terminal V2 = (Vo -Vd3 ) /2 = (Vo – 0.7) /2 Since Vid ≅ 0v , ∴ V1 = V2 Vo = (5.65 *2 ) + 0.7 = 12v.

3. Determine the output waveform for the circuit Where input = 2 Vp sine wave with time period 0.2ms. Answer: a [Reason:] Given circuit is the thevenin equivalent of absolute value output circuit. Therefore, the output will be equal to the input regardless of polarity. Therefore, Vo (+) = Vo (-) = 2 Vp sine wave with 0.2 ms time period. So, the output wave form will be a full wave rectified output of 2v amplitude,

4. What is the alternate method to measure the values of non-sinusoidal waveform other than ac voltmeter?
a) Clipper
b) Clamper
c) Peak detector
d) Comparator

Answer: c [Reason:] A conventional ac voltmeter is designed to measure rms value of the pure sine wave whereas, the peak value of the non-sinusoidal wave forms can be a peak detector.

5. State the condition needed to be satisfied by peak detector for proper operation of circuit.
a) CRd ≤ T/10 and CRL ≥ 10T
b) CRd ≤ 10T and CRL ≥ T/10
c) CRd ≥ T/10 and CRL ≤ 10T
d) CRd ≥ 10T and CRL ≤ T/10

Answer: a [Reason:] For proper operation of the circuit, charging and discharging time constant must satisfy the following: CRd ≤ T/10 and CRL ≥ to 10T.

6. The resistor in the peak detector are used to
a) To maintain proper operation
b) Protect op-amp from damage
c) To get shaped non-sinusoidal waveform
d) None of the mentioned

Answer: b [Reason:] The resistor is used to protect the op-amp against the excessive discharge current, especially when the power supply is switched off.

7. How the recovery time of the op-amp is reduced?
a) Diode is connected at the output of amplifier
c) Forward biased diode resistor
d) Discharge capacitor

Answer: a [Reason:] The diode connected at the output of op-amp conducts during negative half cycle of input voltage. Hence, prevent the op-amp from going into negative saturation. This in turn helps to reduce the recovery time of the op-amp.

8. How to detect the negative peaks of input signals in the peak detector given below? a) Reversing D1 diode
b) Reversing D1 and D2 diodes
c) Reversing D2 diode
d) Charging the positions of D1 and D2

Answer: b [Reason:] The negative peaks of the input signal Vin can be detected by reversing diodes D1 and D2.

9. In the sample and hold circuit, the period during which the voltage across capacitor is equal to input voltage
a) Sample period
b) Hold period
c) Delay period
d) Charging period

Answer: a [Reason:] The time periods of the sample and hold control voltage during which the voltage across capacitor is equal to the input voltage are called sample period.

10. During which period the op-amps output of sample and hold circuits is processed?
a) Delay period
b) Sample and hold period
c) Sample period
d) Hold period

Answer: d [Reason:] Hold period is the period during which the voltage across the capacitor is constant and the output of the op-amp is processed or observed during hold periods.

11. Which IC is mostly preferred for sample and hold circuit?
a) µ771
b) IC741
c) LF398
d) µ351

Answer: c [Reason:] LF398 have significant reduction in size and improved performance and require only an external storage capacitor.

12. Sample and hold circuit are used in
a) Analog to Digital modulation
b) Digital to analog modulation
c) Pulse position modulation
d) All of the mentioned

Answer: d [Reason:] All types of modulation involve taking samples of an input signal and hold on to it last sample value until the input is sampled.

## Linear Integrated MCQ Set 4

1. How the peaking response is obtained?
a) Using a series LC network with op-amp
b) Using a series RC network with op-amp
c) Using a parallel LC network with op-amp
d) Using a parallel RC network with op-amp

Answer: c [Reason:] The peaking response is the frequency response that peaks at a certain frequency. This can be obtained by using a parallel LC network with the op-amp.

2. The expression for resonant frequency of the op-amp
a) fp = 1/[2π×√(LC)].
b) fp = (2π×√L)/C
c) fp = 2π×√(LC)
d) fp = 2π/√(LC)

Answer: a [Reason:] The resonant frequency is also called as peak frequency, which is determined by the combination of L and C. fp = 1/(2π√LC).

3. From the circuit given below find the gain of the amplifier a) 1.432
b) 9.342
c) 5.768
d) 7.407

Answer: d [Reason:] Frequency, fp= 1/[2π×√(LC)] =1/[2π√(0.1µF×8mH)]=1/1.776×10-4= 5.63kHz. => XL = 2πfpL = 2π×5.63kHz×8mH = 282.85. The figure of merit of coil, Qcoil= XL/R1= 282.85/100Ω = 2.8285. ∴ Rp = (Qcoil)2 ×R1 = (2.8285^2)×100Ω= 800Ω. The gain of the amplifier at resonance is maximum and given by AF =-(RF||Rp)/R1 = -(10kΩ||800)/100Ω =-740.740/100 = -7.407.

4. The parallel resistance of tank circuit and for the circuit is given below.Find the gain of the amplifier? a) -778
b) -7.78
c) -72.8
d) None of the mentioned

Answer: b [Reason:] The gain of the amplifier at resonance is the maximum and given by, AF =-(RF||Rp)/ R1 =-[(Rp×RF)/ (RF+Rp)] /R1 = -[ (10kΩ×35kΩ)/ (10kΩ+35kΩ)] /1kΩ => AF =- 7.78kΩ/1kΩ= -7.78.

5. The band width of the peaking amplifier is expressed as
a) BW = (fp× XL)/ (RF+Rp)
b) BW =[ fp×(RF+Rp)× XL ] / (RF×Rp)
c) BW =[ fp×(RF+Rp)] / (RF×Rp)
d) BW = [fp×(RF+Rp) ]/ XL

Answer: b [Reason:] The bandwidth of the peaking amplifier, BW = fp/Qp, where Qp – figure of merit of the parallel resonant circuit = (Rf||Rp)/Xl = (Rf×Rp)/[(Rf+Rp)× Xl] => BW = [fp×(Rf+Rp)× Xl] / (Rf×Rp).

6. Design a peaking amplifier circuit to provide a gain of 10 at a peak frequency of 32khz given L=10mH having 30Ω resistance. Answer: b [Reason:] Given L=10mH and the internal resistance of the inductor R=30Ω. Assume R1=100Ω. The gain times peak frequency= 10×32kHz=320kHz fp= 1/2π√LC => C = 1/[(2π)2× (fp)2×L]= 1/ [(2π)2×(320)2×10mH] = 1/252405.76 = 3.96µF ≅4µF. Qcoil = xL/R =(2πfpL)/R =(2π×320kHz×10mH)/30 = 20096/30 =669.87 => Rp= (Qcoil)2×R = (669.88)2×30 = 13.5MΩ To find Rf, AF= (RF×Rp)/[R1×(RF+Rp)] =>RF = (Af ×Rp ×R1)/ (Rp -AF ×R1) RF = (-10×13.5×106×100) / (13.5×106-(10×100))=1000Ω => RF = 1kΩ. Thus the component values are R1=100Ω, RF= 1kΩ, L=10mH at R=30Ω and C = 4µF.

## Linear Integrated MCQ Set 5

1. Analog phase detector is often referred as
a) Full wave detector
b) Half wave detector
c) Rectifier wave detector
d) None of the mentioned

Answer: b [Reason:] Analog phase detector is called as half wave detector because, the phase information for only one-half of the input waveform is detected and averaged.

2. What happens when VCO output is 90o out of phase with respect to input signal?
a) Perfect lock
b) Attenuation
c) Shift in phase of comparator
d) Error signal is removed

Answer: a [Reason:] The error voltage is zero when the phase shift between the two inputs is 90o. So, for the perfect lock, the VCO output should be 90o out of phase with respect to the input signal.

3. Find the error voltage of phase comparator whose input signal is Vs= Vssin(2πfst) and the output signal Vo= Vosin(2πfot+φ).
a) Ve=[k×(Vs/2)]×[cos(-φ)-cos(2πfot+φ)].
b) Ve=[k×Vs×(Vo/2)]×[cos(-φ)-cos(2πfot+φ)].
c) Ve=[k×Vs×(Vo/2)]×[cos(-φ)+cos(2πfot+φ)].
d) Ve=[k×Vs×Vo]×[cos(-φ)-cos(2πfot+φ)].

Answer: b [Reason:] A phase comparator is basically a multiplier which multiplies the input signal by the VCO signal. Thus, the phase comparator output = Vs×Vo = Vs×Vosin(2πfst)× sin(2πfot+φ) =k×Vs×Vo ×sin(2πfst)×sin(2πfot+φ) Where k – phase comparator gain.= k×Vs×Vo/2[cos(-φ)-cos(2πfot+φ)] When at lock, fs =fo => Ve = Ve={k×Vs× Vo/2}x[cos(-φ)-cos(2πfot+φ)].

4. How to overcome the problem associated with switch type phase detective?
a) Increase loop gain depending on input signal
b) Phase shift is made linear
c) Limit the amplifier of input signal
d) All of the mentioned

Answer: c [Reason:] The problems can be eliminated by limiting the amplifier of the input signal that is converting the input to a constant amplified square wave. This can be achieved by using a balanced modulator used as full wave switching phase detector.

5. If the average error voltage & the phase shift are given as 6.2v & π/4.Determine the phase angle to voltage transfer coefficient of full wave switching phase detector.
a) -0.19
b) -0.09
c) -0.03
d) -0.13

Answer: d [Reason:] The phase angle to voltage transfer coefficient =>kφ = (φ-π/2)/ Ve (avg) =[π/4-π/2]/6.2 =[π-2π/4]/6.2 = -(π/4)/6.2 = -π/24.8 =>kφ = -0.13.

6. When does a digital phase detector can be used, where fo->output frequency, fs->input frequency.
a) Both fo & fs signals should be square wave
b) fo should be square wave & fs can be any non-sinusoidal wave
c) fs should be square wave & fo can be any non-sinusoidal wave
d) Both fo & fs can be any non-sinusoidal wave

Answer: a [Reason:] The XOR gate produces high output when only one of the input signal fo or fs is high. So, to detect high or low value of waveform, square waves are used.

7. The maximum dc output voltage in digital phase detector occurs
a) When the phase difference is π/2
b) When the phase difference is π
c) When the phase difference is 3π/4
d) When the phase difference is 2π

Answer: b [Reason:] The maximum dc output voltage occurs when the phase difference is π, because the output of the XOR gate phase detector remains high throughout.

8. Given the DC output voltage versus phase difference φ curve. Find the conversion gain values. Answer: c [Reason:] The slope gives the conversion gain. Therefore, conversion gain=Vcc/φ =5V/π =1.59V/rad.

9. Which among the following has better capture tracking & locking characteristics?
a) XOR phase detector
b) Edge triggered phase detector
c) Analog phase detector
d) All of the mentioned