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## Linear Integrated MCQ Set 1

1. Which filter attenuates any frequency outside the pass band?
a) Band-pass filter
b) Band-reject filter
c) Band-stop filter
d) All of the mentioned

### View Answer

Answer: a [Reason:] A band- pass filter has a pass band between two cut-off frequencies fH and fL. So, any frequency outside this pass band is attenuated.

2. Narrow band-pass filters are defined as
a) Q < 10
b) Q = 10
c) Q > 10
d) None of the mentioned

### View Answer

Answer: c [Reason:] Quality factor (Q) is the measure of selectivity, meaning higher the value of Q, the narrower its bandwidth.

3. A band-pass filter has a bandwidth of 250Hz and center frequency of 866Hz. Find the quality factor of the filter?
a) 3.46
b) 6.42
c) 4.84
d) None of the mentioned

### View Answer

Answer: a [Reason:] Quality factor of band-pass filter, Q =fc/bandwidth= 566/250=3.46.

4. Find the center frequency of wide band-pass filter
a) fc= √(fh ×fL)
b) fc= √(fh +fL)
c) fc= √(fh -fL)
d) fc= √(fh /fL)

### View Answer

Answer: a [Reason:] In a wide band-pass filter, the product of high and low cut-off frequency is equal to the square of center frequency i.e. ( fc)2 =fH×fL => fc= √(fh×fL).

5. Find out the voltage gain magnitude equation for the wide band-pass filter.
a) AFt×( f/fL)/√[(1+(f/fh)2]×[1+(f/fL)2].
b) AFt/ √{[1+(f/fh)2]×[1+(f/fL)2]}
c) AFt/ √{[1+(f/fh)2]/[1+(f/fL)2]}
d) [AFt/(f/fL)]/ √{[1+(f/fh)2]/[1+(f/fL)2]}

### View Answer

Answer: a [Reason:] The voltage gain magnitude of the band-pass filters equal to the product of the voltage gain magnitudes of high pass and low pass filter.

6. When a second order high pass filter and second order low pass sections are cascaded, the resultant filter is a
a) ±80dB/decade band-pass filter
b) ±40dB/decade band-pass filter
c) ±20dB/ decade band-pass filter
d) None of the mentioned

### View Answer

Answer: b [Reason:] The order of the band-pass filter depends on the order of the high pass and low pass filter sections.

7. Find the voltage gain magnitude of the wide band-pass filter?
Where total pass band gain is=6, input frequency = 750Hz, Low cut-off frequency =200Hz and
high cut-off frequency=1khz.
a) 13.36 dB
b) 12.25 dB
c) 11.71 dB
c) 14.837dB

### View Answer

Answer: d [Reason:] Voltage gain of the filter, |VO/Vin|=[AFt×(f/fL)]/{√[1+(f/fL)2]×[1+f/fL)2]} =[6×(750/20)]/√{[1+(750/200)2]×[1+(750/200)2]} =22.5/√(15.6×1.56) =5.519. |VO/Vin|= 20log(5.519) =14.837dB.

8. Compute the quality factor of the wide band-pass filter with high and low cut-off frequencies equal to 950Hz and 250Hz.
a) 0.278
b) 0.348
c) 0.696
d) 0.994

### View Answer

Answer: c [Reason:] Quality factor Q=√(fh×fL)/(fh-fL) = √(950Hz×250Hz)/(9950Hz-250Hz) =0.696.

9. The details of low pass filter sections are given as fh =10kHz, AF= 2 and f=1.2kHz. Find the voltage gain magnitude of first order wide band-pass filter, if the voltage gain magnitude of high pass filter section is 8.32dB.
a) 48.13dB
b) 10.02dB
c) 14.28dB
d) 65.99dB

### View Answer

Answer: c [Reason:] |VO/Vin|(high pass filter) = 8.32dB=10(8.32/20) =2.606. Therefore, the voltage gain of wide band-pass filter |VO/Vin|= AFt×(f/fL)/√[1+(f/fh)2)]×[1+(f/fL)2)] ={Af/√[(1+(f/fh)2]}×{(Af×f/fL)/√[1+(f/fL)2]} =Aft /√[1+(f/fh)2]×(2.606) = [2/√(1+(1.2kHz/10kHz)2]×( 2.606) = 1.986×2.606 =5.17 =20log×(5.17) =14.28dB.

10. The quality factor of a wide band-pass filter can be
a) 12.6
b) 9.1
c) 14.2
d) 10.9

### View Answer

Answer: b [Reason:] A wide band-pass filter has quality factor less than 10.

11. Design a narrow band-pass filter, with fc=1kHz, Q= 13 and AF=10 (Take C=0.1µF) ### View Answer

Answer: b [Reason:] Given C =0.1µF. Therefore, C1=C2 =0.1µF. R1 =Q/(2π×fc×CAF) =13/( 2π×1kHz×0.1µF×10) =13/6.28 = 2.07 ≅ 2Ω. R2 =Q/{2π×fc×C ×[(2Q2)- AF]} =13/{(2π×1kHz×0.1µF×[2×(132)-10]} = 13/0.2059=63.11 ≅ 63Ω. R3 =Q/(π×fc×C) = 13/(π×1kHz×0.1µF) = 13/3.14×10-4 =41.40kΩ ≅41kΩ.

12. If the gain at center frequency is 10, find the quality factor of narrow band-pass filter
a) 1
b) 2
c) 3
d) None of the mentioned

### View Answer

Answer: c [Reason:] The gain of the narrow band-pass filter must satisfy the condition, AF= 2×Q2 When Q=3, => 2×Q2 =2×(32) =18. => 10<18. Hence condition is satisfied when Q=3.

13. The advantage of narrow band-pass filter is
a) fc can be changed without changing gain
b) fc can be changed without changing bandwidth
c) fc can be changed without changing resistors
d) All of the mentioned

### View Answer

Answer: d [Reason:] As the narrow band-pass filter has multiple filters. The center frequency can be changed to a new frequency without changing the gain or bandwidth and is accomplished by changing the resistor to a new value which is given as R’=R×(fL/fc)2.

## Linear Integrated MCQ Set 2

1. How many types of band elimination filters are present
a) Three
b) Two
c) Four
d) None of the mentioned

### View Answer

Answer: b [Reason:] Band-reject filters are also called as band elimination filters. They are classified into two types. i) Wide band-reject filter and ii) Narrow band-reject filter.

2. Find the wide band-reject filter ### View Answer

Answer: b [Reason:] A wide band-reject filter is made using a low pass filter, a high pass filter and a summing amplifier.

3. A narrow band-reject filter is commonly called as
a) Notch filter
b) Band step filter
c) Delay filter
d) All of the mentioned

### View Answer

Answer: a [Reason:] A narrow band-reject filter is also called as notch filter because of its higher quality factor, Q (>10).

4. Find the expression for notch-out frequency?
a) fN = 2πRC
b) fN = 2π/RC
c) fN = 1/2π×√(R/C)
d) fN = 1/2πRC

### View Answer

Answer: d [Reason:] The notch-out frequency is the frequency at which maximum attenuation occurs: it is given by fN =1/2πRC.

5. The quality factor of passive twin T-network is increased by using
a) Inverting amplifier
b) Non-inverting amplifier
c) Voltage follower
d) Differential amplifier

### View Answer

Answer: c [Reason:] The passive twin T-network has a selectively low figure of merit. The Q of the network can be increased significantly, if it is used with the voltage follower.

6. Find out the application in which narrow band-reject filter can be used?
a) Embedded system
b) Biomedical instrument
c) Digital computer
d) None of the mentioned

### View Answer

Answer: b [Reason:] Notch filters or narrow band-reject filters are used in biomedical instruments for eliminating undesired frequencies.

7. Design 120Hzactive notch filter? ### View Answer

Answer: a [Reason:] Since C value < 0.1µF, assume C=0.68µF Notch Frequency, fn = 1/2πRC. R= 1/(2πfnC)= 1/(2π×120Hz×0.68×10-6) = 1.95kΩ ≅2kΩ. For R/2, parallel of two 2kΩ resistor =>R/2 = 2kΩ||2kΩ =(2×2)/(2+2)=1kΩ. For C/2 , parallel of two 0.68µF capacitor C/2=> 0.68µF + 0.68µF= 1.36µF.

8. Find the application of area where all-pass filters are used?
a) Cathode ray oscilloscope
b) Television
c) Telephone wire
d) None of the mentioned

### View Answer

Answer: c [Reason:] When signals are transmitted in transmission lines like telephone wire, they undergo change in phase, all-pass filters are used to compensate these phase changes.

9. Determine the output voltage for all the all-pass filter and express it in complex form?
a) VO =Vin/ [(1-j2πfRC) /(1+ j2πfRC)].
b) VO =Vin× [(1+j2πfRC) /(1- j2πfRC)].
c) VO =Vin ×[(1- j2πfRC) /(1+ j2πfRC)].
d) None of the mentioned

### View Answer

Answer: c [Reason:] The output voltage of all-pass filter is given as VO =Vin× [(1-j2πfRC) /(1+j2πfRC)] .

10. Determine the input frequency for all-pass filter with phase angle as 62o. Consider the value of resistor and capacitor are 3.3kΩ and 4.7µF.
a) Input frequency= -7.65Hz
b) Input frequency= -6.77Hz
c) Input frequency= -3.89Hz
d) Input frequency= -9.65Hz

### View Answer

Answer: d [Reason:] The phase angle is given as Φ = -2tan-1×(2πfRC) => f=-tanΦ/4πRC =-tan(62o)/(4π×3.3kΩ×4.7µF)= -1.88/0.1948 =-9.65Hz.

11. Determine the angle for given circuit diagram, if the frequency of input signal is 1khz a) -45o
b) -180o
c) -270o
d) -90o

### View Answer

Answer: d [Reason:] Phase angle Φ=-2tan-1×(2πfRC/1) = -2tan-1×(2π×1kHz×16kΩ×0.01µF) = -2tan-1×(1.0048)=-90o.

12. The voltage gain magnitude of all-pass filter is
a) Zero
b) One
c) Infinity
d) None of the mentioned

### View Answer

Answer: b [Reason:] The magnitude of voltage gain of all-pass filter |VO /Vin| = √(1+(2π/RC)2) / √(1+(2 π/RC)2) =1.

13. What happens if the position of R and C are interchanged in the below circuit diagram? a) Vin leads VO
b) Vin lags VO
c) VO leads Vin
d) VO leads Vin

### View Answer

Answer: c [Reason:] For the circuit given, the phase angle changes from 0 to 180o as frequency is varied from 0 to ∞. If the positions of R and C are interchanged, the phase shift and band width input and output becomes positive. That is the output (VO) leads input (Vin).

14. Choose the incorrect statement “In wide band-reject filter” .
a) Low cut-off frequency of low pass filter must be larger than the high cut-off frequency of the high pass filter.
b) Low cut-off frequency of high pass filter must be equal than the high cut-off frequency of the high pass filter.
c) Low cut-off frequency of high pass filter must be smaller than the high cut-off frequency of the low pass filter.
d) None of the mentioned

### View Answer

Answer: d [Reason:] In wide band-reject filter, low cut-off frequency of high pass filter must be larger than the high cut-off frequency of the low pass filter.

## Linear Integrated MCQ Set 3

1. Express the output voltage of digital to analog converter?
a) Vo =KVFS(d12-1+d22-2+….dn2-n)
b) Vo =VFS/k(d12-1+d22-2+….dn2-n)
c) Vo =VFS(d12-1+d22-2+….dn2-n)
d) Vo =K(d12-1+d22-2+….dn2-n)

### View Answer

Answer: a [Reason:] The input is an n-bit binary word D and is combined with the reference voltage VR to give on analog output signal. Mathematically it is described as Vo =KVFS(d12-1+d22-2+….dn2-n) where, K -scaling factor, VFS-full scale output voltage.

2. Why the switches used in weighted resistor DAC are of single pole double throw (SPDT) type?
a) To connect the resistance to reference voltage
b) To connect the resistance to ground
c) To connect the resistance to either reference voltage or ground
d) To connect the resistance to output

### View Answer

Answer: c [Reason:] SPDT are electronic switches controlled by a binary word. If the binary input to a switch is 1, it connects the resistance to the reference voltage and if the input is 0, the switch connects the resistor to ground.

3. Determine the output current for an n-bit weighted resistor DAC?

a) (VR/R )× (do/2 +d1/22 + ……dn/2n)
b) (VR/R )× (d1/21 +d2/22 + ……dn/2n)
c) (VR/R )× (d02/2 +d12/22 + ……dn2/2n)
d) None of the mentioned

### View Answer

Answer: b [Reason:] The output current, Io= I1+I2+….In Io= (VR/2R )×(d1) +(VR/22R)× (d2) ….+(VR/2nR )×(dn) Io =(VR/R)× (d1/21 +d2/22 + ……dn/2n).

4. In a D-A converter with binary weighted resistor, a desired step size can be obtained by
a) Selecting proper value of VFS
b) Selecting proper value of R
c) Selecting proper value of RF
d) All of the mentioned

### View Answer

Answer: c [Reason:] The size of the steps depends on the value of RF, provided that the maximum output voltage does not exceed the saturation level of an op-amp.

5. Determine the Full scale output in a 8-bit DAC for 0-15v range?
a) Full scale output=15.1v
b) Full scale output=15.2v
c) Full scale output=14.5v
d) Full scale output=14.94v

### View Answer

Answer: d [Reason:] Full scale output = (Full scale voltage -LSB) = [15v-(15v/28)] = (15v-0.0586) = 14.94v.

6. Pick out the incorrect statement “In a 3 bit weighted resistor DAC”
a) Although the op-amp is connected in inverting mode, it can also be connected in non-inverting mode
b) The op-amp simply work as a current to voltage converter
c) The polarity of the reference voltage is chosen in accordance with the input voltage
d) None of the mentioned

### View Answer

Answer: c [Reason:] The polarity of the reference voltage is accordance with the type of the switch used. For example, in TTL switches, the reference voltage should be +5v and the output will be negative.

7. What is the disadvantage of binary weighted type DAC?
a) Require wide range of resistors
b) High operating frequency
c) High power consumption
d) Slow switching

### View Answer

Answer: a [Reason:] For better resolution of output, the input binary word length has to be increased. As the number of bit increases, the range of resistance value increases.

8. The smallest resistor in a 12 bit weighted resistor DAC is 2.5kΩ, what will be the largest resistor value?
a) 40.96MΩ
b) 10.24MΩ
c) 61.44 MΩ
d) 18.43MΩ

### View Answer

Answer: b [Reason:] The largest resistor value for 12-bit DAC= 2n×R = 212×2.5kΩ = 4096×2.5kΩ =10.24MΩ.

9. CMOS inverter is used as SPDT switch in resistor DAC and is connected to the op-amp line. Find the output of CMOS, if the input applied is 1
a) Resistance is connected to ground
b) Resistance is connected to input line
c) Resistance is connected to bit line
d) None of the mentioned

### View Answer

Answer: b [Reason:] When Qbar =1, it makes transistor Q1-ON and Q2-OFF. The output of the CMOS inverter is 0v, connecting the resistance R1 to ground.

10. How to overcome the limitation of binary weighted resistor type DAC?
a) Using R-2R ladder type DAC
b) Multiplying DACs
c) Using monolithic DAC
d) Using hybrid DAC

### View Answer

Answer: a [Reason:] Usage wide range of resistors is the limitation of binary weighted resistor type DAC, this can be avoided by using R-2R ladder type DAC Where only two value of resistor are required.

11. Find output voltage equation for 3 bit DAC converter with R and 2R resistor?
a) Vo= -RF [(b2/8R) +(b1/4R) +(b0/2R)].
b) Vo= -RF [(b2/R) +(b1/2R) +(b0/4R)].
c) Vo= -RF [(b2/2R)+(b1/4R) +(b0/8R)].
d) Vo= -RF [(b0/4R)+(b1/2R) +(b2/R)].

### View Answer

Answer: c [Reason:] The output voltage corresponding to all possible combination of binary input in a 3-bit R-2R DAC is given as Vo=-RF [(b2/2R) +(b1/4R) +(b0/8R)].

## Linear Integrated MCQ Set 4

1. Find the basic chemical reaction used for Epitaxial growth? ### View Answer

Answer: c [Reason:] The basic chemical reaction used for epitaxial growth of pure silicon is the hydrogen reduction of silicon tetrachloride.

2. Which component is added to the p-type material in order to get the impurity concentration in epitaxial films?
a) Bi-borane (B2H2)
b) Phosphine (PH3)
c) Boron chloride (BCl3)
d) Phosphorous pentoxide (P2O5)

### View Answer

Answer: a [Reason:] Bi-Borane is used for doping p-type materials and Phosphine is used for doping n-type materials whereas Boron chloride and Phosphorous pentoxide are used for doping during diffusion process.

3. Where are the silicon wafers placed in the reaction chamber for the epitaxial growth process?
a) Cup
b) Boats
c) Ingots
d) Crucible

### View Answer

Answer: b [Reason:] The silicon rods are not directly placed in the reaction chamber instead they are placed on a rectangular graphite rod called boats and then it is heated to 1200oc.

4. Which of the following is used to obtain silicon crystal structure while fabricating Integrating Circuits?
a) Oxidation
b) Epitaxial growth
c) Photolithography
d) Silicon wafer preparations

### View Answer

Answer: b [Reason:] Epitaxial growth is arranging of atoms in single crystal fashion upon a single crystal substrate, so that the resulting layer is an extension of the substrate crystal structure.

5. Why oxidation process is required?
a) To protect against contamination
b) To use it for fabrication various components
c) To prevent diffusion of impurities
d) All of the mentioned

### View Answer

Answer: d [Reason:] Oxidation provides extreme hard protective coating, thus protecting against contamination and by selective etching, it can be made to fabricate components.

6. Mention the chemical reaction for oxidation process
a) Si + 2H2O –> SiO2 + 2H2
b) Si + O2 –> SiO2
c) 2Si + 2H2O –> 2SiO2 + 2H2
d) 2Si + 2H2O + 2O2 –> 2SiO2 + 2H2 + O2

### View Answer

Answer: a [Reason:] For oxidation process, silicon wafers are heated to a high temperature and simultaneously they are exposed to a gas containing H2O or O2 or both.

7. At what temperature should the oxidation process be carried out to get an oxide film of thickness 0.02 to 2µm?
a) 0-105oc
b) 950-1115oc
c) 200-850oc
d) 350-900oc

### View Answer

Answer: b [Reason:] Silicon wafers are raised to a high temperature in the range 950-1115oc and are exposed to gas. The thickness of layer is governed by time, temperature and its moisture content.

8. Oxidation process in silicon planar technology is also called as
a) Photo oxidation
b) Silicon oxidation
c) Vapour oxidation
d) Thermal oxidation

### View Answer

Answer: d [Reason:] The oxidation process is called thermal oxidation process because high temperature is used to grow the oxide layer.

9. In Crzochralski crystal growth process, the materials are heated up to
a) 950oc
b) 1000 oc
c) 1420oc
d) 1200oc

### View Answer

Answer: c [Reason:] The materials are heated above 1420oc which is greater than the silicon melting point.

10. How to obtain silicon ingots of 10-15cm diameter?
a) By crystal pulling process
b) By crystal melting process
c) By crystal growing process
d) All of the mentioned

### View Answer

Answer: a [Reason:] During crystal pulling process, the seed crystal and the crucible rotate in opposite direction, in order to produce ingots of circular cross section (diameter of 10/15cm normally obtained).

11. If the thickness of wafer after all polishing steps in silicon wafer preparation is 23-40 mils. Find its raw cut slice thickness?
a) 16-32 mils
b) 23-40 mils
c) 8-12 mils
d) None of the mentioned

### View Answer

Answer: a [Reason:] Usually the silicon wafer obtained has a very rough surface due to slicing operation. So, these wafers undergo a number of polishing steps to produce flat and smooth polished surface. Therefore, the thickness of wafers will be reduced from its raw cut slice.

## Linear Integrated MCQ Set 5

1. Free running multivibrator is also called as
a) Stable multivibrator
b) Voltage control oscillator
c) Square wave oscillator
d) Pulse stretcher

### View Answer

Answer: b [Reason:] Free running multivibrator operates at a frequency which is determined by an external tuning capacitor and a resistor. On applying a dc control voltage the frequency can be shifted on either sides. This frequency deviation is directly proportional to the dc control voltage and hence it is called as ‘voltage controlled oscillator’.

2. The output voltage of phase detector is
a) Phase voltage
b) Free running voltage
c) Error voltage
d) None of the mentioned

### View Answer

Answer: c [Reason:] The phase detector compares the input frequency with the feedback frequency and produces output dc voltage called as error voltage.

3. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) All of the mentioned

### View Answer

Answer: c [Reason:] In the phase-locked, the output frequency is exactly same as the input signal frequency. So the circuit tracks any change in the input frequency through its repetitive action.

4. Match the list I with list II which represents the three stages of phase locked loop.(PLL)

 List I List II 1.Before input frequency applied i. PLL-Phase locked state 2.When the input frequency applied ii.PLL=Free running state 3.After input frequency applied iii. PLL-Capture mode

a) 1-ii, 2-iii, 3-i
b) 1-iii, 2-ii, 3-i
c) 1-i, 2-ii, 3-iii
d) 1-ii, 2-i, 3-iii

### View Answer

Answer: a [Reason:] Before the input is applied, the PLL is in a free running state. Once the input frequency is applied, the VCO frequency start to change & PLL is said to be in capture mode. When the VCO frequency continues to change until it is equal to the input frequency, the PLL is said to be in phase locked state.

5. What is the function of low pass filter in phase-locked loop?
a) Improves low frequency noise
b) Removes high frequency noise
c) Tracks the voltage changes
d) Changes the input frequency

### View Answer

Answer: b [Reason:] The output voltage of a phase detector is a dc voltage and is often referred to as error voltage. This output is applied to the low pass filter which removes the high frequency noise and produces a dc level.

6. What is the need to generate corrective control voltage?
a) To maintain the lock
b) To track the frequency change
c) To shift the VCO frequency
d) All of the mentioned

### View Answer

Answer: d [Reason:] The output frequency(fo) of VCO is identical to input frequency(fs) except for a finite phase difference(φ), which generates a corrective control voltage to shift VCO frequency from fo to fs, thereby maintains the lock once locked and PLL tracks the frequency changes of the input signal.

7. At what range the PLL can maintain the lock in the circuit?
a) Lock in range
b) Input range
c) Feedback loop range
d) None of the mentioned

### View Answer

Answer: a [Reason:] The change in frequency of the incoming signal can be tracked when the PLL is locked. So, the range of frequencies over which PLL maintains the lock with the incoming signal is called as the lock in range.

8. The pull-in time depends on
a) Initial phase and frequency difference between two sign
b) Overall loop gain
c) Loop filter characteristics
d) All of the mentioned

### View Answer

Answer: d [Reason:] The pull-in time depends on the above mentioned characteristics to establish lock in the PLL circuit. .woocommerce-message { background-color: #98C391 !important; }