Generic selectors
Exact matches only
Search in title
Search in content
Search in posts
Search in pages
Filter by Categories
nmims post
Objective Type Set
Online MCQ Assignment
Question Solution
Solved Question
Uncategorized

## Linear Integrated MCQ Set 1

1. At what condition the digital to analog conversion is made? a) Va > Vd
b) Va ≤ Vd
c) Va ≥ Vd
d) Va ≠ Vd

Answer: b [Reason:] When Va < Vd, the output of the comparator becomes low and the AND gate is disabled. This stops the counting at that time and the digital output of the counter represents the analog input voltage.

2. If a input at Va is 1010, then find the correct conversion sequence for the given circuit.
a)

 Input signal SAR output at different stages comparator output 1010 1000 1 1100 0 1010 1 1011 0 1010

b)

 Input signal SAR output at different stages comparator output 1010 0001 0 0010 1 0011 0 1010 1

c)

 Input signal SAR output at different stages comparator output 1010 1111 0 1011 0 1001 1 1010 1

d) None of the mentioned

Answer: a [Reason:] The given circuit is a successive approximation register and it finds the required value of each bit trial and error method. When the conversion start SAR set MSB d1=1 with other bits zero. So, trial code is 1000. If Va(1010) is greater than DAC output (1000). Then MSB is left `1′ and the next lower significant bit is made `1′ and further tested.

3. The Integrating type converters are used in
a) Digital meter
b) Panel meter
c) Monitoring system
d) All of the mentioned

Answer: d [Reason:] The Integrating type converters are used in application such as digital meter, panel meter and monitoring system where the conversion accuracy is critical.

4. In integrating type ADCs, the
a) Input voltage is proportional to input averaged over the integration period
b) Output voltage is proportional to input averaged over the integration period
c) Output voltage is proportional to sum of input voltage
d) Input voltage is proportional to sum of input voltage

Answer: b [Reason:] Since the integrating type ADC do not require sample and hold circuit at the input. The change in input during conversion will not affect the output code and is proportional to the value of the input averaged over the integration period.

5. Which type of ADC is chosen for noisy environment?
a) Successive approximation ADC
b) Dual slope
c) Charge balancing ADC
d) All of the mentioned

Answer: c [Reason:] The main advantage of these converters is that it is possible to transmit frequency even in noisy environment or in isolated form.

6. How to overcome the drawback of the charge balancing ADC?
a) By using precision integrator
b) By using Voltage to frequency converter
c) By using voltage comparator
d) By using dual slope converter

Answer: d [Reason:] Charge balancing ADC depend up on RC product whose value cannot be easily maintained with temperature and time. This is eliminated using dual slope ADC as it is independent of R, C and T.

7. Which among the following has long conversion time?
a) Servo converter
b) Dual ramp converter
c) Flash converter
d) None of the mentioned

Answer: b [Reason:] The main disadvantage of dual slope ADC is the long conversion time. For instance, if 2n-T=1/50 is used to reject line pick-up, the conversion time will be 20ms.

8. In which application dual slop converter are used.
a) Thermocouple
b) Digital panel meter
c) Weighting scale
d) All of the mentioned

Answer: b [Reason:] Dual slope converters are particularly suitable for accurate measurement of slow varying signals.

9. A dual slope has the following specifications:
16bit counter; Clock rate =4 MHz; Input voltage=12v; Output voltage =-7v and Capacitor=0.47µF.
If the counters have cycled through 2n counts, determine the value of resistor in the integrator.
a) 60kΩ
b) 50kΩ
c) 120kΩ
d) 100kΩ

Answer: a [Reason:] Time period of the dual slope integrator, △(t) =t2-t1 =2ncounts/clock rate =216/4Mhz=16.38ms. For integration, △Vo=(-1/RC)×V×( t2-t1) => RC = -(12v/-7v) ×16.38ms=28.08ms ∴ R= 28.08ms =59744 ≅60kΩ.

10. A 12 bit dual ramp generation has a maximum output voltage of +12v. Compute the equivalent digital number for the analog signal of +6v.
a) 1000000000
b) 10000000000
c) 1000000000000
d) 100000000000

Answer: d [Reason:] since Va =VR (N/2n) so the digital count N= 2n×(Va/VR) N= 212×(6/12v) = 4096×0.5 =2048. Binary equivalent for 2048 => 100000000000.

## Linear Integrated MCQ Set 2

1. How an AC amplifier can be powered by a single supply voltage, produces voltage swing?
a) By inserting a voltage divider at the inverting input
b) By inserting a voltage divider at the non-inverting input
c) By inserting a voltage divider at the output
d) By inserting a voltage divider at the feedback circuit

Answer: b [Reason:] A positive dc level is intentionally inserted using a voltage-divider network at the non-inverting input terminal, so that output can swing both positively as well as negatively.

2. Given below are the circuits connected to the non-inverting input terminal of AC amplifier. Choose the circuit which produces positive output swing equal the negative? Answer: b [Reason:] The circuit is generally a positive dc level (+Vcc/2), so the positive output swing will be equal to negative and this is accomplished by selecting R2 = R3.

3. What is the output waveform at the point VO1 in the given circuit? (Take R1=1kΩ and RF=5kΩ)  Answer: c [Reason:] The input is applied at the inverting terminal so, the AC output will be riding on a DC level of (+Vcc/2) volts and will be inverted. Vo = -(RF/R1)×Vin = -(5kΩ/1kΩ)×6Vp = 30Vp sinewave.

4. The input waveform of an AC non-inverting amplifier with single supply is given below. Find the output waveform?  Answer: b [Reason:] The coupling capacitor at the output blocks the AC output signal riding on a DC level of (+Vcc/2) volts and the resultant waveform will be AC. In non-inverting amplifier, the output will be of the same phase as that of input signal.

5. Find the maximum output voltage swing of an AC inverting amplifier using op-amp 741C?
a) +15Vpp
b) ±15Vpp
c) ±13Vpp
d) +13Vpp

Answer: a [Reason:] The value of power supply for 741 op-amp=±15v. Therefore, the ideal maximum output voltage swing for an AC amplifier with single power supply = +Vcc = +15v.

6. Determine the lower cut-off frequency of the circuit. a) 21.3Hz
b) 12.15Hz
c) 1.35Hz
d) None of the mentioned

Answer: d [Reason:] The input resistance of the amplifier is RIF =(R2 ||R3) || [ri×(1+AB)] –> equ 1 As [ri×(1+AB)] >> R2 => Therefore, equ 1 becomes RIF ≅ R2 || R3 = 100kΩ || 100kΩ = (100×100)/(100+100) = 50kΩ. => Rin = Ro = 150Ω. ∴ Lower cut off frequency, fL= 1/[2πCi×(RIF+Ro)] = 1/[2π×0.47µF×(50kΩ+150Ω)] = 6.75Hz.

7. In differential op-amp configuration a subtractor is called as
a) Summing amplifier
b) Difference amplifier
c) Scaling amplifier
d) All of the mentioned

Answer: c [Reason:] In a subtractor input signals can be scaled to the desired values by selecting appropriate values for the external resistors. Therefore, this circuit is referred to as scaling amplifier.

## Linear Integrated MCQ Set 3

1. An electrical filter is a
a) Phase-selective circuit
b) Frequency-selective circuit
c) Filter-selective circuit
d) None of the mentioned

Answer: b [Reason:] An electric filter is often a frequency selective circuit that passes a specified band of frequencies and blocks or alternates signal of frequencies outside this band.

2. Filters are classified as
a) Analog or digital
b) Passive or active
c) Audio or radio frequency
d) All of the mentioned

Answer: d [Reason:] Filters are classified based on the design technique (analog or digital), elements used for construction (active or passive) and operating range (audio or radio frequency).

3. Why inductors are not preferred for audio frequency?
a) Large and heavy
b) High power dissipation
c) High input impedance
d) None of the mentioned

Answer: a [Reason:] At audio frequencies, inductor becomes problematic, as the inductors become large, heavy and expensive.

4. The problem of passive filters is overcome by using
a) Analog filter
b) Active filter
c) LC filter
d) A combination of analog and digital filters

Answer: b [Reason:] The active filters enclose as a capacitor in the feedback loop and avoid using inductors, this way inductorless active filter are obtained.

5. What happens if inductors are used in low frequency applications?
a) Enhance inductor usage
b) No losses occurs
c) Degrades inductor performance
d) Low power dissipation

Answer: c [Reason:] For low frequency applications more number of turns of wire must be used, which in turn adds to the series resistance degrading inductor’s performance.

6. Find out the incorrect statement about active and passive filters.
a) Gain is not attenuated in active filter
b) Passive filters are less expensive
c) Active filter does not cause loading of source
d) Passive filters are difficult to tune or adjust

Answer: b [Reason:] Typically active filters are more economical than passive filters. This is because of the variety of cheaper op-amp and the absence of inductor’s.

7. What are the most commonly used active filters?
a) All of the mentioned
b) Low pass and High pass filters
c) Band pass and Band reject filters
d) All-pass filters

Answer: a [Reason:] All the mentioned filters use op-amp as active element and capacitors & resistors as passive elements.

8. Choose the op-amp that improves the filter performance.
a) µA741
b) LM318
c) LM101A
d) MC34001

Answer: b [Reason:] LM318 is a high speed op-amp that improves the filter’s performance through increased slew rate and higher unity gain-bandwidth.

9. Ideal response of filter takes place in
a) Pass band and stop band frequency
b) Stop band frequency
c) Pass band frequency
d) None of the mentioned

Answer: c [Reason:] The ideal response indicates the practical filter response and it lies within the pass band frequencies.

10. Find out the low pass filter from the given frequency response characteristics. Answer: a [Reason:] A low pass filter has a constant gain from 0Hz to high cut-off frequency fH.

## Linear Integrated MCQ Set 4

1. Which filter type is called a flat-flat filter?
a) Cauer filter
b) Butterworth filter
c) Chebyshev filter
d) Band-reject filter

Answer: b [Reason:] The key characteristic of the butterworth filter is that it has a flat pass band as well as stop band. So, it is sometimes called a flat-flat filter.

2. Which filter performs exactly the opposite to the band-pass filter?
a) Band-reject filter
b) Band-stop filter
c) Band-elimination filter
d) All of the mentioned

Answer: d [Reason:] A band reject is also called as band-stop and band-elimination filter. It performs exactly the opposite to band-pass because it has two pass bands: 0 < f < fL and f > fH.

3. Given the lower and higher cut-off frequency of a band-pass filter are 2.5kHz and 10kHz. Determine its bandwidth.
a) 750 Hz
b) 7500 Hz
c) 75000 Hz
d) None of the mentioned

Answer: b [Reason:] Bandwidth of a band-pass filter is Bandwidth= fH– fL=10kHz-2.5kHz=7.5kHz=7500Hz.

4. In which filter the output and input voltages are equal in amplitude for all frequencies?
a) All-pass filter
b) High pass filter
c) Low pass filter
d) All of the mentioned

Answer: a [Reason:] In all-pass filter, the output and input voltages are equal in amplitude for all frequencies. This filter passes all frequencies equally well and with phase shift and between the two function of frequency.

5. The gain of the first order low pass filter
a) Increases at the rate 20dB/decade
b) Increases at the rate 40dB/decade
c) Decreases at the rate 20dB/decade
d) Decreases at the rate 40dB/decade

Answer: c [Reason:] The rate at which the gain of the filter changes in the stop band is determined by the order of filter. So, for a low pass filter the gain decreases at the rate of 20dB/decade.

6. Which among the following has the best stop band response?
a) Butterworth filter
b) Chebyshev filter
c) Cauer filter
d) All of the mentioned

Answer: c [Reason:] The cauer filter has a ripple pass band and a ripple stop band. So, generally cauer filter gives the best stop band response among the three.

7. Determine the order of filter used, when the gain increases at the rate of 60dB/decade on the stop band.
a) Second-order low pass filter
b) Third-order High pass filter
c) First-order low pass filter
d) None of the mentioned

Answer: b [Reason:] The gain increases for high pass filter. So, for a third order high pass filter the gain increases at the rate of 60dB/decade in the stop band until f=fL.

8. Name the filter that has two stop bands?
a) Band-pass filter
b) Low pass filter
c) High pass filter
d) Band-reject filter

Answer: a [Reason:] A band-pass filter has two stop bands: 1) 0 < f < fL and 2) f > fH.

9. The frequency response of the filter in the stop band.
i. Decreases with increase in frequency
ii. Increase with increase in frequency
iii. Decreases with decrease in frequency
iv. Increases with decrease in frequency
a) i and iv
b) ii and iii
c) i and ii
d) ii and iv

Answer: c [Reason:] The order of frequency of the filter in the stop band determines either steady decreases or increases or both with increase in frequency.

## Linear Integrated MCQ Set 5

1. Which is the most striking feature in monolithic integrated circuit transistor?
a) Collector contact is present at the bottom of IC
b) Collector contact is present at the top of IC
c) Collector contact is absent
d) Collector contact is present on one of the sides of IC

Answer: b [Reason:] In IC transistor, the collector contact has to be taken from the top because collector is isolated from the substrate and next isolation island by reverse biased diodes.

2. Why monolithic IC transistor is preferred over discrete planar epitaxial transistor?
a) Due to structural difference
b) Increase in VCE (sat) and collector series resistor
c) Improvement in circuit performance
d) All of the mentioned

Answer: d [Reason:] As the collector contact is present on the top of IC transistor, it makes structural difference. Hence, it increases collector series resistance and VCE(sat) of device. From this, circuit performance is highly improved as matched transistor can be obtained.

3. Name the process that is used to overcome the increase in collector series resistance, which occurs due to the presence of collector contact at the top of integrated transistor.
a) Buried n+ layer
b) Buried p+ layer
c) Triple diffused layer
d) Buried epitaxial layer

Answer: a [Reason:] The value of collector series resistance of an integrated transistor can be easily reduced by a process known as “buried layer” or “Buried n+ layer”.

4. What is the reason for using Lateral pnp transistor in Integrated Circuits?
a) Requires simple process control
b) Simultaneous fabrication of pnp and npn transistors
c) Provide good isolation
d) Miniaturization and cost reduction

Answer: b [Reason:] During the p-type base diffusion for npn transistor, two adjacent p-regions are diffused to form the emitter and collector region of the lateral pnp transistor (n-type epitaxial layer is used as base of the pnp transistor).Thus, pnp and npn transistors are fabricated simultaneously.

5. Which of the following transistor has the limitation, due to the requirement of additional fabrication steps and design consideration?
a) Vertical pnp transistor
b) Lateral pnp transistor
c) Triple diffused pnp transistor
d) Substrate pnp transistor

Answer: c [Reason:] In triple diffused pnp transistor fabrication process, an extra p-type diffusion is added to a standard npn-transistor after the n-diffusion to obtain a pnp transistor. However, the usefulness of such a structure is not used due to its limitation.

6. The ‘buried layer’ reduces collector series resistance by providing,
a) A low resistivity current path from n-type layer to n+ contact layer
b) A low resistivity current path from p-type layer to n+ contact layer
c) A high resistivity current path from n-type layer to n+ contact layer
d) A high resistivity current path from p-type layer to n+ contact layer

Answer: a [Reason:] A heavily doped n+ region is sandwiched between the n-type epitaxial collector and p-type substrate. This buried n+ region provide a low resistivity current path from active collector region (n-type layer) to the collector contact (n+ contact layer). In effect, the n+ layer shunt n-layer of collector region with respect to flow of current, thus effectively reduces the collector resistance.

7. At what potential, the substrate of a vertical pnp transistor should be kept to attain good isolation?
a) Same potential
b) Positive potential
c) Different potential
d) Negative potential

Answer: d [Reason:] The limitation of vertical pnp transistor is that, collector has to be held at a fixed negative potential, as substrate is to be held at the most negative potential in the circuit for providing good isolation.

8. Which method is used in the fabrication of pnp transistor?
a) Vertical substrate pnp
b) Triple diffused pnp
c) Lateral pnp
d) All of the mentioned

Answer: d [Reason:] pnp transistors in Integrated Circuits are fabricated in one of the following three ways.

9. State the correct reason for neglecting pnp transistor.
a) Increase in the series collector resistance of pnp transistor
b) Parasitic capacitance appears between collector and substrate
c) Current gain of pnp transistor is as low as 1.5 to 30
d) None of the mentioned

Answer: c [Reason:] Lateral pnp transistor has inferior characteristic as the base width is usually larger controlled by lateral diffusion of p-type impurities and photographic limitations during mask marking and alignment. Therefore, pnp transistor normally gives current gain as low as 1.5 to 30 compared to 50-300 for the npn transistor.

10. The diffusion of collector impurities in npn transistor should be small because,
a) No additional diffusion or masking steps required
b) Bandwidth is controlled by lateral diffusion of p-type impurity
c) Collector need not be kept at negative potential
d) None of the mentioned

Answer: d [Reason:] Generally, n-type impurities have smaller diffusion constant than p-type impurities, the n-type collector moves very little while p-type moves appreciably. Therefore, the diffusion coefficient of the collector impurities should be as small as possible to avoid the movement of the collector junction.

11. The advantage of Multi-emitter transistor is
a) To reduce fabrication steps
b) To save chip area
c) To lower design consideration
d) To provide linear output

Answer: b [Reason:] In Mutli-emitter transistor n+ emitter is diffused at three places in the p-type base. Thus, it is possible to save chip area and enhance component density of an IC.

12. Which transistor is best suitable to achieve very fast switching in digital circuits?
a) Lateral pnp transistor
b) Schottky transistor
c) Multi-emitter transistor
d) NPN transistor

Answer: b [Reason:] Fast switching can be achieved, if the transistor is prevented from entering into saturation. In schottky transistor, schottky diode is used to clamp between base and collector. Whenever the base current increases to saturation, the diode conducts. Thus, the base to collector voltage drops to 0.4v (less than VBE(cut-in)=0.5) and the transistor does not enter into saturation .

13. Choose the appropriate value of diode to get a speedy diode from the given values of storage time (n) in sec and forward voltage (V γ).
a) n = 56 , V γ = 0.96
b) n = 100 , V γ = 0.92
c) n = 9 , V γ = 0.85
d) n = 53 , V γ = 0.95