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## Linear Integrated MCQ Set 1

1. A Differential Amplifier should have collector resistor’s value (RC1 & RC2) as
a) 5kΩ, 5kΩ
b) 5Ω, 10kΩ
c) 5Ω, 5kΩ
d) 5kΩ, 10kΩ

Answer: a [Reason:] The values of collector current will be equal in differential amplifier (RC1=RC2).

2. A Differential Amplifier amplifies
a) Input signal with higher voltage
b) Input voltage with smaller voltage
c) Sum of the input voltage
d) None of the Mentioned

Answer: d [Reason:] The purpose of differential amplifier is to amplify the difference between two signals.

3. The value of emitter resistance in Emitter Biased circuit are RE1=25kΩ & RE2=16kΩ. Find RE
a) 9.756kΩ
b) 41kΩ
c) 9.723kΩ
d) 10kΩ

Answer: a [Reason:] In emitter biased circuit, RE1 & RE2 is connected in parallel combination. ⇒ RE = RE1 II RE2 = (RE1× RE2)/(RE1+RE2) = (25kΩ×16kΩ)/(25kΩ+16kΩ) = 9.7561kΩ.

4. If output is measured between two collectors of transistors, then the Differential amplifier with two input signal is said to be configured as
a) Dual Input Balanced Output
b) Dual Input Unbalanced Output
c) Single Input Balanced Output
d) Dual Input Unbalanced Output

Answer: a [Reason:] When two input signals are applied to base of transistor, it is said to be Dual Input. When both collectors are at same DC potential with respect to ground, then it is said to be Balance Output.

5. A differential amplifier is capable of amplifying
a) DC input signal only
b) AC input signal only
c) AC & DC input signal
d) None of the Mentioned

Answer: c [Reason:] Direct connection between stages removes the lower cut off frequency imposed by coupling capacitor; therefore it can amplify both AC and DC signal.

6. In ideal Differential Amplifier, if same signal is given to both inputs, then output will be
a) Same as input
b) Double the input
c) Not equal to zero
d) Zero

Answer: d [Reason:] In ideal amplifier, Output voltage ⇒ Vout = Vin1-Vin2.

7. Find the Single Input Unbalance Output configuration in following circuit diagrams :
a)
b)
c)
d)

Answer: c [Reason:] Circuit c has only single input (V1) and output is measure only at one of the collector with respect to ground.

8. An emitter bias Dual Input Balanced Output differential amplifier has VCC=20v, β=100, VBE=0.7v, RE=1.3kΩ. Find IE
a) 7.42mA
b) 9.8mA
c) 10mA
d) 8.6mA

Answer: a [Reason:] Emitter current can be found out by substituting the values in the equation, ⇒ IE = (VEE-VBE)/(2RE) = (20v-07v)/(2×1.3kΩ) = 7.42mA.

9. Find IC, given VCE=0.77v, VCC=10v, VBE=0.37v and RC=2.4kΩ in Dual Input Balanced Output differential amplifier
a) 0.4mA
b) 0.4A
c) 4mA
d) 4A

Answer: c [Reason:] Substitute the values in collector to emitter voltage equation, VCE= VCC+ VBE-RC IC ⇒IC = (VCC-VCE+VBE)/RC = (10v-0.77v+0.37v)/2.4kΩ = 4mA

10. Find the correct match

ConfigurationVoltage gain and Input resistance
1. Single Input Unbalanced Outputi. Ad = Rc/re , Ri1 Ri2 = 2βacRE
2. Dual Input Balanced Outputii. Ad= Rc/2re , Ri1 Ri2 = 2βacRE
3. Single Input Balanced Outputiii. Ad= Rc/re , Ri = 2βacRE
4. Dual Input Unbalanced Outputiv. Ad = Rc/2re , Ri = 2βacRE

a) 1-i , 2-iii, 3-iv, 4-ii
b) 1-iv, 2-ii, 3-iii, 4-i
c) 1-ii, 2-iv, 3-i , 4-iii
d) 1-iii, 2-i, 3-ii, 4-iv

Answer: d [Reason:] Properties of differential amplifier circuit configuration.

11. Obtain the collector voltage, for collector resistor (RC) =5.6kΩ, IE=1.664mA and VCC=10v for single input unbalanced output differential amplifier
a) 0.987v
b) 0.682v
c) 0.555v
d) None of the mentioned

Answer: b [Reason:] Substitute the given values in collector voltage equation, VC= VCC – RC×IC ⇒ VC= 10v – 5.6kΩ×1.664mA (∵ IC ≅ IE ) ⇒ VC= 0.682v.

12. For the circuit shown below, determine the Output voltage (Assume β=5, differential input resistance=12 kΩ)

a) 4.33v
b) 2.33v
c) 3.33v
d) 1.33v

Answer: c [Reason:] From the circuit dig, RC=10kΩ, Vin1= 1.3v and Vin2=0.5v, Differential input resistance = 2 βre, ⇒ 12kΩ = 2×5×Re ⇒ Re = 1.2 kΩ Output voltage Vo = RC/2Re(Vin1-Vin2) ⇒ Vo = 10kΩ/(2 ×1.2kΩ) × (1.3v-0.5v) ⇒ Vo = 3.33v.

13. In a Single Input Balanced Output Differential amplifier, given VCC=15v, RE = 3.9kΩ, VCE=2.4 v and re=250Ω. Determine Voltage gain
a) 26
b) 56
c) 38
d) 61

Answer: a [Reason:] In single Input Balance Output amplifier, ⇒ IE = (VEE-VBE)/2RE =(15v-0.7v)/(2×3.9kom)= 1.83mA (∵VCC=VEE) From the equation, VCE = VCC +VBE-RC×IC ⇒ RC = (14.3v – 2.4v)/1.83mA = 6.5kΩ The voltage gain, Vo ⇒ Vo = RC/re = 6.5kΩ/250Ω = 26(no units).

## Linear Integrated MCQ Set 2

1. Which is not the internal circuit of operational amplifier?
a) Differential amplifier
b) Level translator
c) Output driver
d) Clamper

Answer: d [Reason:] Clamper is an external circuit connected at the output of Operational amplifier, which clamp the output to desire DC level.

2. The purpose of level shifter in Op-amp internal circuit is to
b) Increase impedance
c) Provide high gain
d) Decrease input resistance

Answer: a [Reason:] The gain stages in Op-amp are direct coupled. So, level shifter is used for adjustment of DC level.

3. How a symmetrical swing is obtained at the output of Op-amp
a) Providing amplifier with negative supply voltage
b) Providing amplifier with positive voltage
c) Providing amplifier with positive& negative voltage
d) None of the mentioned

Answer: c [Reason:] For example, consider a single voltage supply +15v. During positive half cycle the output will be +5v and -10v during negative half cycle. Therefore, the maximum peak to peak output swing, -5v (-10v) = -15v (Asymmetrical swing). So, to get symmetrical swing both positive and negative supply voltage with bias point fixed suitably is required.

4. What is the purpose of differential amplifier stage in internal circuit of Op-amp?
a) Low gain to differential mode signal
b) Cancel difference mode signal
c) Low gain to common mode signal
d) Cancel common mode signal

Answer: d [Reason:] Any undesired noise, common to both of the input terminal is suppressed by differential amplifier.

5. Which of the following is not preferred for input stage of Op-amp?
a) Dual Input Balanced Output
b) Differential Input Single ended Output
d) Single Input Differential Output

Answer: c [Reason:] Cascaded DC amplifier suffers from major problem of drift of the operating point, due to temperature dependency of the transistor.

6. What will be the emitter current in a differential amplifier, where both the transistor are biased and matched? (Assume current to be IQ)
a) IE = IQ/2
b) IE = IQ
c) IE = (IQ)2/2
d) IE = (IQ)2

Answer: a [Reason:] Due to symmetry of differential amplifier circuit, current IQ divides equally through both transistors.

7. From the circuit, determine the output voltage (Assume αF=1)

a) VO1=3.9v , VO2=12v
b) VO1=12v , VO2=3.9v
c) VO1=12v , VO2=0v
d) VO1=3.9v , VO2=-3.9v

Answer: b [Reason:] The voltage at the common emitter ‘E’ will be -0.7v, which make Q1 off and the entire current will flow through Q2. ⇒ VO1 = VCC VO2= VCC-αF×IQ×RC, ⇒ VO1 = 12v , VO2=12v-1×3mA×2.7k = 3.9v.

8. At what condition differential amplifier function as a switch
a) 4VT < Vd < -4VT
b) -2VT ≤ Vd ≤ 2VT
c) 0 ≤ Vd < -4VT
d) 0 ≤ Vd ≤ 2VT

Answer: a [Reason:] For Vd > 4VT, the output voltage are VO1 = VCC, VO2= VCC-αF IQRC. Therefore, a transistor Q1 will be ON and Q2 will be OFF. Similarly for Vd> -4VT, both transistors Q2 & Q1 will be ON.

9. For Vd > ±4VT, the function of differential amplifier will be
a) Switch
b) Limiter
c) Automatic gain control
d) Linear Amplifier

Answer: b [Reason:] At this condition, input voltage of the amplifier is greater than ±100mv and thus acts as a limiter.

10. Change in value of common mode input signal in differential pair amplifier make
a) Change in voltage across collector
b) Slight change in collector voltage
c) Collector voltage decreases to zero
d) None of the mentioned

Answer: a [Reason:] In differential amplifier due to symmetry, both transistors are biased and matched. Therefore, Voltage at each collector will be same.

11. Find collector current IC2, given input voltages are V1=2.078v & V2=2.06v and total current IQ=2.4mA. (Assume α=1)

a) 0.8mA
b) 1.6mA
c) 0.08mA
d) 0.16mA

Answer: a [Reason:] Collector current, IC2F×IQ/(1+eVd⁄VT), VT = Volts equivalent of temperature = 25mv, ⇒ Vd = V1-V2 =2.078v-2.06v=0.018v (equ1) Substituting equation 1, ⇒ Vd/VT = 0.018v/25mv = 0.72v (equ2) Substituting equation 2, ⇒ IC2= 1×2.4mA/(1+e0.72) = 2.4mA/(1+2.05) = 0.8mA.

12. A differential amplifier has a transistor with β0= 100, is biased at ICQ = 0.48mA. Determine the value of CMRR and ACM, if RE =7.89kΩ and RC = 5kΩ.
a) 49.54 db
b) 49.65 d
c) 49.77 db
d) 49.60 db

Answer: b [Reason:] Differential mode gain, ADM= -gmRC and Common mode gain, ⇒ ACM= -(gmRC)/(1+2gmRE) (for β0≫1). Substituting the values, ⇒ gm= ICQ/VT = 0.48mA/25mv=19.2×10-3Ω-1 ⇒ ADM= -gm×RC= -19.2×10-3Ω-1×5kΩ= -96 ⇒ ACM= -(gmRC)/(1+2gmRE)= -(19.2×10-3Ω-1×5kΩ) /(1+2×-⇒ 19.2×10-3Ω-1×7.89kΩ) = -0.3158 CMRR = -96/-0.3158= 303.976 =20log⁡303.976 =49.65db

## Linear Integrated MCQ Set 3

1. How are the arbitrary signal represented, that are applied to the input of transistor? (Assume common mode signal and differential mode signal to be VCM & VDM respectively).
a) Sum of VCM & VDM
b) Difference of VCM & VDM
c) Sum and Difference of VCM & VDM
d) None of the mentioned

Answer: c [Reason:] In practical situation, arbitrary signal are signal are represented as Sum and Difference of common mode signal and differential mode signal.

2. How the differential mode gain is expressed using ‘h’ parameter for a single ended output?
a) – hfeRC/hie
b) 1/2×(hfeRC)/hie
c) – 1/2×hfeRC
d) None of the mentioned

Answer: b [Reason:] Formula for differential mode gain using ‘h’ parameter model for a single ended output.

3. Find Common Mode Rejection Ration, given gm =16MΩ-1, RE=25kΩ
a) 58 db
b) 40 db
c) 63 db
d) 89 db

Answer: a [Reason:] Formula for Common Mode Rejection Ration, CMRR= 1+2gmRE, ⇒ CMRR = 1+(2×16MΩ-1×25kΩ) = 801 = 20log⁡801 = 58.07 db.

4. In differential amplifier the input are given as V1=30sin⁡Π(50t)+10sin⁡Π(25t) , V2=30sin⁡Π(50t)-10 sin⁡Π(25t), β0 =200,RE =1kΩ and RC = 15kΩ. Find the output voltages V01, V02 & gm=4MΩ-1
a) V01=-60[10 sin⁡Π(25t) ]-6.637[30sin⁡Π(50t) ], V02=60[10 sin⁡Π(25t) ]-6.637[30sin⁡Π(50t) ].
b) V01=-6.637[10 sin⁡Π(25t) ]-60[30sin⁡Π(50t) ], V02=6.637[10 sin⁡Π(25t) ]-60[30sin⁡Π(50t) ].
c) V01=-60[30 sin⁡Π(50t) ]-6.637[10sin⁡Π(25t) ], V02=60[30 sin⁡Π(50t) ]-6.637[10sin⁡Π(25t) ].
d) V01=-6.637[30 sin⁡Π(50t) ]-60[10sin⁡Π(25t) ], V02=6.637[30 sin⁡Π(50t) ]-60[10sin⁡Π(25t) ].

Answer: a [Reason:] Differential mode gain, ADM = -gm RC, ⇒ ADM = -4MΩ-1×15kΩ = 60 ⇒ rΠ0/gm =200/4MΩ-1 =50kΩ Common mode gain, ACM=-βo×RC/rΠ+(βO+1)×RE ⇒ ACM =-200×15kΩ/50kΩ+2(1+200)×1kΩ=-6.637 Common mode signal, VCM=(V1+V2)/2= 30sin⁡Π(50t) Differential mode signal, VDM=(V1-V2)/2= 10 sin⁡Π(25t) Output voltages are given as ⇒ V01=ADM)× VDM)+ ACM× VCM = -60[10 sin⁡Π(25t)]-6.637[30sin⁡Π(50t)], ⇒ V02=-ADM× VDM+ ACM× VCM = 60[10 sin⁡Π(25t)]-6.637[30sin⁡Π(50t)].

5. If the value of Common Mode Rejection Ratio and Common Mode Gain are 40db and -0.12 respectively, then determine the value of differential mode gain
a) 0.036
b) -1.2
c) 4.8
d) 12

Answer: d [Reason:] Common mode rejection ratio, CMRR =log-1×(40/20) = 100 ⇒ CMRR =(∣ADM∣/ ∣ACM∣) ⇒ ∣ADM∣ =100×0.12 = 12.

6. To increase the value of CMRR, which circuit is used to replace the emitter resistance Re in differential amplifier?
a) Constant current bias
b) Resistor in parallel with Re
c) Resistor in series with Re
d) Diode in parallel with Re

Answer: a [Reason:] Constant current bias offers extremely large resistor under AC condition and thus provide high CMRR value.

7. What is the purpose of diode in differential amplifier with constant current circuit?
a) Total current independent on temperature
b) Diode is dependent of temperature
c) Transistor is depend on temperature
d) None of the mentioned

Answer: a [Reason:] The base emitter voltage of transistor (VBE) in constant current circuit by 2.5mv/oc, thus diode also has same temperature. Hence two variations cancel each other and total current IQ become in depend of temperature.

8. How to improve CMRR value
a) Increase common mode gain
b) Decrease common mode gain
c) Increase Differential mode gain
d) Decrease differential mode gain

Answer: b [Reason:] For a large CMRR value, ACM should be small as possible.

9. Define total current (IQ) equation in differential amplifier with constant current bias current
a) IQ=1/R3×(VEE/R1+R2)
b) IQ =(VEE×R2)/(R1+R2)
c) IQ=1/R3×(VEE×R2/R1+R2)
d) IQ)=R3×(VEE/R1+R2)

Answer : c [Reason:] The equation for total current is obtained by applying Kirchhoff’s Voltage Law to constant current circuit in differential amplifier.

10. Constant current source in differential amplifier is also called as
a) Current Mirror
b) Current Source
c) Current Repeaters
d) All of the mentioned

Answer: a [Reason:] The output current is reflection or mirror of the reference input current. Therefore, the constant current source circuit referred as Current Mirror.

11. When will be the mirror effect valid
a) β≫1
b) β=1
c) β<1
d) β≠1

Answer: a [Reason:] If value of β is used in the equation, IC=β/(β+2)×Iref. It almost become unity and the output current become equal to reference current.

12. Calculate the value of reference current and input resistor for current mirror with IC=1.2μA & VCC=12v. Assume β=50.
a) 1.248mA, 9kΩ
b) 1.248mA, 9.6kΩ
c) 1.248mA, 9.2kΩ
d) 1.2mA, 9.6kΩ

Answer: a [Reason:] We know that collector current, IC=β/(β+2)×Iref, ⇒ Iref=(β+2)/β×IC= (50+2)/50× 1.2μA = 1.248mA ⇒ Iref=(VCC-VBE)/R1 ⇒ R1=(12v-07v)/1.248mA = 9.05kΩ.

## Linear Integrated MCQ Set 4

1. Free running frequency of Astable multivibrator?
a) f=1.45/(RA+2RB)C
b) f=1.45(RA+2RB)C
c) f=1.45C/(RA+2RB)
d) f=1.45 RA/( RA+RB)

Answer: a [Reason:] The frequency of the Astable multivibrator is T=0.69(RA+2RB)C. Therefore, f = 1/T =1.45/(RA+2RB)C.

2. Find the charging and discharging time of 0.5µF capacitor.

a) Charging time=2ms; Discharging time=5ms
b) Charging time=5ms; Discharging time=2ms
c) Charging time=3ms; Discharging time=5ms
d) Charging time=5ms; Discharging time=3ms

Answer: b [Reason:] The time required to charge the capacitor is tHigh=0.69(RA+RB)C =0.69(10kΩ+5kΩ)x0.5µF =5ms. The time required to discharge the capacitor is tLow=0.69xRC =0.69x5kΩx0.5µF=2ms.

3. Astable multivibrator operating at 150Hz has a discharge time of 2.5m. Find the duty cycle of the circuit.
a) 50%
b) 75%
c) 95.99%
d) 37.5%

Answer: d [Reason:] Given f=150Hz.Therefore,T=1/f =1/150 =6.67ms. ∴ Duty cycle, D%=(tLow/T) x 100% = (2.5ms/6.67ms)x100% = 37.5%.

4. Determine the frequency and duty cycle of a rectangular wave generator.

a) Frequency=63.7kHz; Duty cycle=50%
b) Frequency=53.7kHz; Duty cycle=55%
c) Frequency=43.7kHz; Duty cycle=50%
d) Frequency=60kHz; Duty cycle=55%

Answer: b [Reason:] Frequency=1.45/(RA+RB)C . Where RA=100Ω+50Ω=150Ω, RB=100Ω+20Ω=120Ω. =>∴f=1.45/((150+120)x0.1µF) = 53703Hz = 53.7kHz. Duty cycle, D% = [RB/(RA+RB)] x 100% = 120Ω/(150Ω +120Ω) x 100% = 0.55×100% = 55%.

5. How to achieve 50% duty cycle in adjustable rectangular wave generator? (Assume R1 –> Resistor connected between supply and discharge and R2 –> Resistor connected between discharge and trigger input.)
a) R1 < R2
b) R1 > R2
c) R1 = R2
d) R1 ≥ R2

Answer: c [Reason:] The equation of duty cycle, D = R2/(R1 + R2). If R1 is made equal to R2 then 50% duty cycle is achieved.

6. How to obtain symmetrical waveform in Astable multivibrator?
a) Use clocked RS flip-flop
b) Use clocked JK flip-flop
c) Use clocked D-flip-flop
d) Use clocked T-flip-flop

Answer: b [Reason:] Symmetrical square wave can be obtained by adding a clocked JK flip-flop to the output of Astable multivibrator. The clocked flip-flop acts as a binary divider to the times output and produces 50% duty cycle without any restriction on the choice of resistors.

7. Determine the output frequency of the circuit.

a) 1450Hz
b) 1333Hz
c) 1871Hz
d) 1700Hz

Answer: c [Reason:] The output frequency of the frequency shift keying generator is f=1.45/[(RA||RC)+2(RB)]xC = 1.45/[(2.3kΩ||2.3kΩ) + (2×3.3kΩ)] x 0.1µF = 1.45/{[(2.3×2.3)/(2.3+2.3)] + 6.6kΩ}x0.1µF = 1.45/(7.75×10-4) = 1870.9 ≅ 1871Hz.

8. How does a monostable multivibrator used as frequency divider?
a) Using square wave generator
b) Using triangular wave generator
c) Using sawtooth wave generator
d) Using sine wave generator

Answer: a [Reason:] Monostable multivibrator can be used as a frequency divider when a continuously triggered monostable circuit is triggered using a square wave generator. Provided the timing interval is adjusted to be longer than the period of triggering square wave input signal.

## Linear Integrated MCQ Set 5

1. Determine the time period of a monostable 555 multivibrator.
a) T = 0.33RC
b) T = 1.1RC
c) T = 3RC
d) T = RC

Answer: b [Reason:] The time period of a monostable 555 timer is T = RC×ln(1/3) = 1.1.RC.

2. Find monostable vibrator circuit using 555 timer.

Answer: a [Reason:] When 555 timer is configured in monostable operation, the trigger input is applied through pin2 whereas, upper comparator threshold (pin6) & discharge (pin7) are shorted and connected at the output.

3. How to overcome mistriggering on the positive pulse edges in the monostable circuit?
a) Connect a RC network at the input
b) Connect an integrator at the input
c) Connect a differentiator at the input
d) Connect a diode at the input

Answer: c [Reason:] To prevent the mistrigger on positive pulse edges, a resister & capacitor combined of 10kΩ and 0.001µF at the input to form a differentiator The circuit shows the differentiator to be connected between trigger input and the +VCC.

4. A monostable multivibrator has R = 120kΩ and the time delay T = 1000ms, calculate the value of C?
a) 0.9µF
b) 1.32µF
c) 7.5µF
d) 2.49µF

Answer: c [Reason:] Time delay for a monostable multivibrator, T = 1.1RC => C = T/(1.1R) = 1000ms/(1.1×120kΩ) = 7.57µF.

5. Which among the following can be used to detect the missing heart beat?
a) Monostable multivibrator
b) Astable multivibrator
c) Schmitt trigger
d) None of the mentioned

Answer: a [Reason:] A monostable multivibrator can be used as a missing pulse detector by connecting a transistor between trigger inputs. If a pulse misses, the discharge trigger input goes high & transistor become cut-off and the output goes low. So, this type of circuit can be used to detect missing heart beat.

6. A 555 timer in monostable application mode can be used for
a) Pulse position modulation
b) Frequency shift keying
c) Speed control and measurement
d) Digital phase detector

Answer: c [Reason:] In monostable operation mode, if input trigger pulses are generated from a rotating wheel, the circuit will determine the wheel speed whenever it drops below a predetermined value. Therefore, it can be used for speed control and measurement.

7. How can a monostable multivibrator be modified into a linear ramp generator?
a) Connect a constant current source to trigger input
b) Connect a constant current source to trigger output
c) Replace resistor by constant current source
d) Replace capacitor by constant current source

Answer: c [Reason:] The resistor R of the monostable circuit is replaced by a constant current source. So, that the capacitor is charged linearly and generates ramp signal.

8. Determine time period of linear ramp generator using the specifications
RE = 2.7kΩ, R1 =47kΩ , R2 100kΩ , C= 0.1µF, VCC =5v.

a) 8ms
b) 4ms
c) 2ms
d) 1ms

Answer: d [Reason:] The time period of the linear ramp generator, T= [(2/3)×(VCC×RE)×(R1+ R2)×C]/{(R1×VCC)-[VBE×(R1+R2)]} = {(2/3)×5v×[2.7kΩ×(4.7kΩ+ 100kΩ)]×(0.1µF)}/{[(47kΩ)×5v]-[(0.7)×(47kΩ+100kΩ)]} =>T= 132.3/132.100 =1.0015×10-3 = 1ms.

9. What will be the output, if a modulating input signal and continuous triggering signal are applied to pin5 and pin22 respectively in the following circuit?

a) Frequency modulated wave form
b) Pulse width modulated wave form
c) Both pulse and frequency modulated wave form
d) None of the mentioned

Answer: b [Reason:] On application of continuous trigger at pin22 and a modulated input signal at pin5, a series of output pulses are obtained. The duration of which depends on the modulating signal. Also in the pulse duration, only the duty cycle varies, keeping the frequency same as that of the continuous input pulse train trigger.

## Linear Integrated MCQ Set 6

1. How many control lines are present in analog to digital converter in addition to reference voltage?
a) Three
b) Two
c) One
d) None of the mentioned

Answer: b [Reason:] ADC usually has two additional control lines 1. Start input-tell ADC when to start conversion. 2. EOC- end of conversion.

2. Find out the integrating type analog to digital converter?
a) Flash type converter
b) Tracking converter
c) Counter type converter

c) Both integrating and direct type ADC
d) None of the mentioned

Answer: b [Reason:] Integrating type ADC performs conversion in an indirect manner by first changing the analog input signal to a linear function of time or frequency and then to a digital code.

4. Which A/D converter is considered to be simplest, fastest and most expensive?
a) Servo converter
d) All of the mentioned

Answer: c [Reason:] The simplest possible A/D converter is flash type converter and is expensive for high degree of accuracy.

5. The flash type A/D converters are called as
a) Parallel non-inverting A/D converter
b) Parallel counter A/D converter
c) Parallel inverting A/D converter
d) Parallel comparator A/D converter

Answer: d [Reason:] The flash type A/D converter are also called as parallel comparator A/D converter because the purpose of the circuit is to compare the analog input voltage with each node voltage.

6. What is the advantage of using flash type A/D converter?
a) High speed conversion
b) Low speed conversion
c) Nominal speed conversion
d) None of the mentioned

Answer: a [Reason:] Flash type ADC has the advantage of high speed as the conversion takes place simultaneously rather than sequentially. Typical conversion time is 100nanosecond or less.

7. The number of comparator required for flash type A/D converter
a) Triples for each added bit
b) Reduce by half for each added bit
c) Double for each added bit
d) Doubles exponentially for each added bit

Answer: c [Reason:] The number of comparator required almost doubles for each added bit. For example – 2 -bit ADC requires three comparators, 3 -bit ADC needs seven comparators and a 4 -bit ADC requires fifteen comparators.

8. Drawback of counter type A/D converter
a) Counter clears automatically
b) More complex
c) High conversion time
d) Low speed

Answer: d [Reason:] In counter type ADC counter frequency is kept low enough to give sufficient time for DAC to settle and for the comparator for respond. So, low speed is the most serious drawback.

9. Calculate the conversion time of a 12-bit counter type ADC with 1MHz clock frequent to convert a full scale input?
a) 4.095 µs
b) 4.095ms
c) 4.095s
d) None of the mentioned

Answer: b [Reason:] conversion time = 2n -1 clock periods = (12n-1) = 4.095ms.

10. In a servo tracking A/D converter, the input voltage is greater than the DAC output signal at this condition
a) The counter count up
b) The counter count down
c) The counter back and forth
d) None of the mentioned

Answer: a [Reason:] In servo converter, the circuit consist of an up/down counter with comparator controlling direction of the count. So, if the input voltage is greater than DAC output signal, the output of comparator goes high and counter is caused to count up.

11. At what condition error occurs in the servo tracking A/D Converter?
a) Slow change input
b) Rapid change in input
c) No change in input
d) All of the mentioned

Answer: b [Reason:] As long as the analog input changes slowly, the tracking A/D converter will be within one LSB of the corrected value. When the input changes rapidly, the tracking A/D converter cannot keep up with change and error occurs.

12. How many clock pulses do a successive approximation converter requires for obtaining a digital output.
a) Twelve
b) Six
c) Eight
d) None of the mentioned