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Interview MCQ Set 1

1. Which of the following is the highest priority usage among them?
a) second transfer cycle of a processor extension data transfer
b) third transfer cycle of a processor extension data transfer
c) hold request
d) second byte transfer of 2-byte transfer at an odd address

View Answer

Answer: d [Reason:] The second byte transfer of 2-byte transfer at an odd address, is the highest priority usage among the given usages.

2. The highest priority usage than any other usage is
a) transfer with LOCK (active low) signal
b) hold request
c) processor extension data transfer
d) data transfer performed by EU (execution unit)

View Answer

Answer: a [Reason:] The transfer with LOCK (active low) signal is the highest priority usage, than any other usage.

3. The lowest priority usage among the following is
a) hold request
b) processor extension data transfer
c) prefetch operation to fetch and arrange next instruction bytes in queue
d) data transfer performed by EU for instruction execution

View Answer

Answer: c [Reason:] The order of priority usages, starting from highest one to the lowest one, is given as 1. transfer with LOCK (active low) signal 2. second byte transfer of 2-byte transfer at an odd address 3. second or third transfer cycle of a processor extension data transfer 4. HOLD request 5. processor extension data transfer 6. data transfer performed by EU (execution unit) 7. prefetch operation to fetch and arrange next instruction bytes in queue.

4. As a response to the valid bus hold request, the bus is pushed into
a) TH (hold) state
b) Ts (status) state
c) Tc (command) state
d) Ti (idle) state

View Answer

Answer: a [Reason:] 80286 local bus is relinquished for another bus master, if a valid bus hold request is received at the HOLD input pin. As a response to a valid bus hold request, the bus is pushed into TH state.

5. The bus arbiter relinquishes
a) Address
b) M/IO (active low)
c) COD/INTA (active low)
d) All of the mentioned

View Answer

Answer: d [Reason:] The address, M/IO (active low) and COD/INTA (active low) are relinquished by bus arbiter.

6. A valid HOLD request is ascertained only after the completion of
a) 34 clockcycles
b) 24 clockcycles and 80286 is SET
c) 34 clockcycles and 80286 is SET
d) 34 clockcycles and 80286 is RESET

View Answer

Answer: d [Reason:] Only after 34 clockcycles, after the 80286 is reset, a valid HOLD request should be ascertained.

7. The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of
a) first INTA (active low) pulse from 80286
b) second INTA (active low) pulse from 80286
c) third INTA (active low) pulse from 80286
d) none of the mentioned

View Answer

Answer: a [Reason:] In response to the first INTA (active low) pulse from 80286, the master PIC 8259A decides, which of its slave interrupt controllers is to return the vector address.

8. The slave (which is selected) sends the vector on data bus after the
a) first INTA (active low) pulse from 80286
b) second INTA (active low) pulse from 80286
c) third INTA (active low) pulse from 80286
d) none of the mentioned

View Answer

Answer: b [Reason:] The interrupt acknowledge sequence consists of two INTA (active low) pulses. After the second pulse, the selected slave sends the vector on D0-D7 data lines, and 80286 reads it.

9. The signal of 82C288, that enables the cascade address drivers, during INTA cycles is
a) DEN
b) DT/R (active low)
c) MCE
d) MB

View Answer

Answer: c [Reason:] The MCE (Master Cascade Enable) signal of 82C288 enables the cascade address drivers during INTA cycles, to select the slave using the local address bus.

10. The LOCK (active low) signal is activated during
a) Ti of first INTA cycle
b) Ts of first INTA cycle
c) Th of second INTA cycle
d) Ts of second INTA cycle

View Answer

Answer: b [Reason:] The LOCK (active low) signal is activated during Ts of first INTA cycle.

11. The number of idle states (Ti), that are allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] The 80286 allows three idle states (Ti) between the two INTA cycles, to meet the 8259A speed and cascade address output delay.

Interview MCQ Set 2

1. The decoder unit in fetch-decode unit, converts the instructions into
a) executable statements
b) machine language statements
c) MMX instructions
d) micro operations

View Answer

Answer: d [Reason:] The decoder unit converts the fetched instructions into micro operations.

2. The logical source(s) and logical destination(s) that the micro operation has respectively are
a) 2,2
b) 1,3
c) 3,1
d) 3,2

View Answer

Answer: c [Reason:] Each microoperation contains two logical sources and one logical destination.

3. The microoperations that are converted by decoder are directly transferred to
a) decoder register
b) dispatch-execute unit
c) retire unit
d) register alias table

View Answer

Answer: d [Reason:] The microoperations are sent to the register alias table(RAT). The RAT translates the logical register references to the physical register set actually available in the CPU.

4. The pool of instructions that are fetched is stored in an addressable memory called
a) tristate buffer
b) branch target buffer
c) reorder buffer
d) order buffer

View Answer

Answer: c [Reason:] The pool of instructions that are fetched is stored in an array of content addressable memory called reorder buffer.

5. The unit that performs scheduling of instructions by determining the data dependencies is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none

View Answer

Answer: b [Reason:] The dispatch-execute unit performs scheduling of instructions by determining the data dependencies after which the microoperations of the scheduled instructions are executed in the execution unit.

6. The unit that reads the instruction pool and removes the microoperations which have been executed instruction pool is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) decoding unit

View Answer

Answer: c [Reason:] The retire unit reads the instruction pool containing the instructions and removes the microoperations which have been executed instruction pool.

7. The speed of Pentium-Pro when compared to that of Pentium is
a) equal
b) twice
c) thrice
d) two-third

View Answer

Answer: b [Reason:] The features incorporated in Pentium-Pro enhances the speed of Pentium-Pro and is twice as that of Pentium.

8. Which of the following is not supported by Pentium-Pro?
a) multiple branch prediction
b) mmx instruction set
c) speculative execution
d) none

View Answer

Answer: b [Reason:] The Pentium-Pro does not support the MMX instruction set.

9. The feature of Pentium II is
a) high cache
b) operates at 2.8 volts
c) supports intel’s MMX instructions
d) all of the mentioned

View Answer

Answer: d [Reason:] The Pentium II has higher cache and it can operate at 2.8 volts, thereby reducing power consumption. The most important change of Pentium II is that it can support Intel’s MMX instructions.

10. The results of speculative instruction execution is stored in
a) visible CPU registers
b) permanent memory
c) temporary memory
d) none

View Answer

Answer: c [Reason:] The results of speculative instruction execution should not be stored in CPU registers and are temporarily stored, since they may have to be discarded, in case if there is a branch instruction before these speculative instruction execution.

Interview MCQ Set 3

1. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
d) none of the mentioned

View Answer

Answer: c [Reason:] The logic required for implementing a program must be visualised clearly which is possible by flowchart and algorithm.

2. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register

View Answer

Answer: b [Reason:] Only one memory operand can be specified in one instruction.

3. The instruction that is not possible among the following is
a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H

View Answer

Answer: c [Reason:] 8-bit or 16-bit operand cannot be used as destination operand.

4. The instruction that is not possible among the following is
a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].

View Answer

Answer: d [Reason:] Both the operands cannot be memory operands.

5. Both the operands source and destination of an instruction cannot be
a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location

View Answer

Answer: c [Reason:] Since destination operand should not be an immediate data.

6. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers

View Answer

Answer: d [Reason:] Segment registers are not allowed as operands for arithmetic and logical instructions.

7. The operands of an instruction cannot be
a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands

View Answer

Answer: b [Reason:] Both the operands should not be immediate operands and memory operands.

Interview MCQ Set 4

1. Sampling rate conversion by the rational factor I/D is accomplished by what connection of interpolator and decimator?
a) Parallel
b) Cascade
c) Convolution
d) None of the mentioned

View Answer

Answer: b [Reason:] A sampling rate conversion by the rational factor I/D is accomplished by cascading an interpolator with a decimator.

2. Which of the following has to be performed in sampling rate conversion by rational factor?
a) Interpolation
b) Decimation
c) Either interpolation or decimation
d) None of the mentioned

View Answer

Answer: a [Reason:] We emphasize that the importance of performing the interpolation first and decimation second, is to preserve the desired spectral characteristics of x(n).

3. Which of the following operation is performed by the blocks given the figure below?
tough-digital-signal-processing-questions-answers-q3
a) Sampling rate conversion by a factor I
b) Sampling rate conversion by a factor D
c) Sampling rate conversion by a factor D/I
d) Sampling rate conversion by a factor I/D

View Answer

Answer: d [Reason:] In the diagram given, a interpolator is in cascade with a decimator which together performs the action of sampling rate conversion by a factor I/D.

4. The Nth root of unity WN is given as:
a) ej2πN
b) e-j2πN
c) e-j2π/N
d) ej2π/N

View Answer

Answer: c [Reason:] We know that the Discrete Fourier transform of a signal x(n) is given as tough-digital-signal-processing-questions-answers-q4 Thus we get Nth rot of unity WN= e-j2π/N

5. Which of the following is true regarding the number of computations requires to compute an N-point DFT?
a) N2 complex multiplications and N(N-1) complex additions
b) N2 complex additions and N(N-1) complex multiplications
c) N2 complex multiplications and N(N+1) complex additions
d) N2 complex additions and N(N+1) complex multiplications

View Answer

Answer: a [Reason:] The formula for calculating N point DFT is given as tough-digital-signal-processing-questions-answers-q5 From the formula given at every step of computing we are performing N complex multiplications and N-1 complex additions. So, in a total to perform N-point DFT we perform N2 complex multiplications and N(N-1) complex additions.

6. Which of the following is true?
tough-digital-signal-processing-questions-answers-q6

View Answer

Answer: b [Reason:] If XN represents the N point DFT of the sequence xN in the matrix form, then we know thattough-digital-signal-processing-questions-answers-q6a

7. What is the DFT of the four point sequence x(n)={0,1,2,3}?
a) {6,-2+2j-2,-2-2j}
b) {6,-2-2j,2,-2+2j}
c) {6,-2+2j,-2,-2-2j}
d) {6,-2-2j,-2,-2+2j}

View Answer

Answer: c [Reason:] The first step is to determine the matrix W4. By exploiting the periodicity property of W4 and the symmetry property tough-digital-signal-processing-questions-answers-q7

8. If X(k) is the N point DFT of a sequence whose Fourier series coefficients is given by ck, then which of the following is true?
a) X(k)=Nck
b) X(k)=ck/N
c) X(k)=N/ck
d) None of the mentioned

View Answer

Answer: a [Reason:] The Fourier series coefficients are given by the expression tough-digital-signal-processing-questions-answers-q8

9. What is the DFT of the four point sequence x(n)={0,1,2,3}?
a) {6,-2+2j-2,-2-2j}
b) {6,-2-2j,2,-2+2j}
c) {6,-2-2j,-2,-2+2j}
d) {6,-2+2j,-2,-2-2j}

View Answer

Answer: d Answer: Given x(n)={0,1,2,3} We know that the 4-point DFT of the above given sequence is given by the expression tough-digital-signal-processing-questions-answers-q5 In this case N=4 =>X(0)=6,X(1)=-2+2j,X(2)=-2,X(3)=-2-2j.

10. If W4100=Wx200, then what is the value of x?
a) 2
b) 4
c) 8
d) 16

View Answer

Answer: c [Reason:] We know that according to the periodicity and symmetry property, 100/4=200/x=>x=8.

Interview MCQ Set 5

1. What is the signal x(n) whose z-transform X(z)=log(1+az-1);|z|>|a|?
tough-digital-signal-processing-questions-answers-2-q1

View Answer

Answer: c [Reason:] tough-digital-signal-processing-questions-answers-2-q1a

2. If Z{x1(n)}=X1(z) and Z{x2(n)}=X2(z) then Z{x1(n)*x2(n)}=?
a) X1(z).X2(z)
b) X1(z)+X2(z)
c) X1(z)*X2(z)
d) None of the mentioned

View Answer

Answer: a [Reason:] According to the convolution property of z-transform, the z-transform of convolution of two sequences is the product of their respective z-transforms.

3. What is the convolution x(n) of the signals x1(n)={1,-2,1} and x2(n)={1,1,1,1,1,1}?
a) {1,1,0,0,0,0,1,1}
b) {-1,-1,0,0,0,0,-1,-1}
c) {-1,1,0,0,0,0,1,-1}
d) {1,-1,0,0,0,0,-1,1}

View Answer

Answer: d [Reason:] tough-digital-signal-processing-questions-answers-2-q3

4. If Z{x1(n)}=X1(z) and Z{x2(n)}=X2(z) then what is the z-transform of correlation between the two signals?
a) X1(z).X2(z-1)
b) X1(z).X2(z-1)
c) X1(z).X2(z)
d) X1(z).X2(-z)

View Answer

Answer: b [Reason:] We know that rx1x2(l)=x1(l)*x2(-l) Now Rx1x2(z)=Z{x1(l)}.Z{x2(-l)}=X1(z).X2(z-1).

5. If x(n) is causal, then lim┬(z→∞)X(z)=?
a) x(-1)
b) x(1)
c) x(0)
d) Cannot be determined

View Answer

Answer: c [Reason:] According to the initial value theorem, X(z)=x(0)+x(1)z -1+x(2)z-2+…. When z→∞, z -n tends to 0 because n>0. So lim┬(n→∞)⁡〖X(z)〗=x(0).

6. If Z{x(n)}=X(z) and the poles of X(z) are all inside the unit circle, then the final value of x(n) as n→∞ is given by i.e., lim┬(n→∞)x(n)=?
tough-digital-signal-processing-questions-answers-2-q6

View Answer

Answer: a [Reason:] According to the Final Value theorem of z-transform we have, tough-digital-signal-processing-questions-answers-2-q6a

7. What is the z-transform of the signal x(n)=δ(n-n0)?
a) zn0
b) z-n0
c) zn-n0
d) zn+n0

View Answer

Answer: b [Reason:] From the definition of z-transform, tough-digital-signal-processing-questions-answers-2-q7

8. If X(z) is the z-transform of the signal x(n), then what is the z-transform of x*(n)?
a) X(z*)
b) X*(z)
c) X*(-z)
d) X*(z*)

View Answer

Answer: d [Reason:] According to the conjugation property of z-transform, we have Z{x*(n)}= X*(z*).

9. If x(n) is an imaginary sequence, then the z-transform of the real part of the sequence is:
a) 1/2[X(z)+X*(z*)].
b) 1/2[X(z)-X*(z*)].
c) 1/2[X(-z)-X*(z*)].
d) 1/2[X(-z)+X*(z*)].

View Answer

Answer: a [Reason:] If x(N) is an imaginary sequence, then the real part of x(n) is given as Real{x(n)}= 1/2[x(n)+x*(n)]. According to linearity property of z-transform, we get Z{ Real{x(n)}}= 1/2[X(z)+X*(z*)].

10. What is the signal whose z-transform is given as tough-digital-signal-processing-questions-answers-2-q10
a) x1(n)*x2(n)
b) x1(n)*x2(-n)
c) x1(n).x2(n)
d) x1(n)*x2*(n)

View Answer

Answer: c [Reason:] From the convolution property in z-domain we have, tough-digital-signal-processing-questions-answers-2-q10a

11. What is the z-transform of the signal x(n)= x1(n).x2*(n)?
tough-digital-signal-processing-questions-answers-2-q11

View Answer

Answer: b [Reason:] We know that Z{x*(n)}=X*(z*) Now from the multiplication property in time domain we get, tough-digital-signal-processing-questions-answers-2-q10a

12. If x1(n)={1,2,3} and x2(n)={1,1,1}, then what is the convolution sequence of the given two signals?
a) {1,2,3,1,1}
b) {1,2,3,4,5}
c) {1,3,5,6,2}
d) {1,2,6,5,3}

View Answer

Answer: d [Reason:] Given x1(n)={ 1,2,3}=>X1(z)=1+2z -1+3z -2 x2(n){1,1,1}=>X2(z)=1+z -1+z -2 Now from the convolution in time domain property of z-transform, we have Z{ x1(n)* x2(n)}= X1(z). X2(z) => X(z)=1+2z-1+6z-2+5z-3+3z-4 =>x(n)={1,2,6,5,3}.

13. What is the z-transform of the signal x(n)=cos(jω0n)u(n)?
tough-digital-signal-processing-questions-answers-2-q13

View Answer

Answer: c [Reason:] By Euler’s identity, the given signal x(n) can be written astough-digital-signal-processing-questions-answers-2-q13a

14. What is the z-transform of the signal defined as x(n)=u(n)-u(n+N)?
tough-digital-signal-processing-questions-answers-2-q14

View Answer

Answer: d [Reason:] tough-digital-signal-processing-questions-answers-2-q14a

15. What is the z-transform of the signal x(n)=[5(3n)-9(7n)]u(n)?
tough-digital-signal-processing-questions-answers-2-q15

View Answer

Answer: a [Reason:] tough-digital-signal-processing-questions-answers-2-q15a