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Interview MCQ Set 1

1. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD

View Answer

Answer: d [Reason:] The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL.

2. The Carry flag is undefined after performing the operation
a) AAA
b) ADC
c) AAM
d) AAD

View Answer

Answer: d [Reason:] Since the operation AAD is performed before division operation is performed, the carry flag, auxiliary flag and overflow flag are undefined.

3. The instruction that performs logical AND operation and the result of the operation is not available is
a) AAA
b) AND
c) TEST
d) XOR

View Answer

Answer: c [Reason:] In the TEST instruction, the logical AND operation is performed and the result is not stored but flags are affected.

4. In the RCL instruction, the contents of the destination operand undergoes function as
a) carry flag is pushed into LSB & MSB is pushed into carry flag
b) carry flag is pushed into MSB & LSB is pushed into carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into carry flag
d) parity flag is pushed into MSB & LSB is pushed into carry flag

View Answer

Answer: a [Reason:] In RCL(Rotate right through carry), for each operation, the carry flag is pushed into LSB and the MSB of the operand is pushed into carry flag.

5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS

View Answer

Answer: b [Reason:] The instruction to which the REP is prefix, is executed repeatedly until CX register becomes zero. When CX becomes zero, the execution proceeds to the next instruction in sequence.

6. Match the following

a) MOvSB/SW       1) loads AL/AX register by content of a string
b) CMPS           2) moves a string of bytes stored in source to destination
c) SCAS           3) compares two strings of bytes or words whose length is stored in CX register
d) LODS           4) scans a string of bytes or words

a) a-3,b-4,c-2,d-1
b) a-2,b-1,c-4,d-3
c) a-2,b-3,c-1,d-4
d) a-2,b-3,c-4,d-1

View Answer

Answer: d [Reason:] By using the string instructions, the operations on strings can be performed.

7. The instructions that are used to call a subroutine from a main program and return to the main program after execution of called function are
a) CALL,JMP
b) JMP,IRET
c) CALL,RET
d) JMP,RET

View Answer

Answer: c [Reason:] At each CALL instruction, the IP and CS of the next instruction is pushed onto stack, before the control is transferred to the procedure.At the end of procedure the RET instruction must be executed to retrieve the stored contents of IP & CS registers from stack.

8. The instruction that unconditionally transfers the control of execution to the specified address is
a) CALL
b) JMP
c) RET
d) IRET

View Answer

Answer: b [Reason:] In this the control transfers to the address specified in the instruction and flags are not affected by this instruction.

9. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold

View Answer

Answer: d [Reason:] Only an interrupt request or Reset will force the 8086 processor to come out of the ‘halt’ state.

10. NOP instruction introduces
a) Address
b) Delay
c) Memory location
d) None of the mentioned

View Answer

Answer: b [Reason:] NOP is the No operation. It means that the processor performs no operation for the clock cycle and thus there exists a delay.

11. Which of the following is not a machine controlled instruction?
a) HLT
b) CLC
c) LOCK
d) ESC

View Answer

Answer: b [Reason:] Since CLC is a flag manipulation instruction where CLC stands for Clear Carry Flag.

Interview MCQ Set 2

1. If the stack flag is set, and condition code bit C1=1, then the stack is
a) full
b) overflown
c) underflown
d) empty

View Answer

Answer: b [Reason:] If the stack flag is set, and condition code bit C1=1, then the stack has overflown.

2. If the stack flag is set, and condition code bit C1=0, then the stack is
a) full
b) overflown
c) underflown
d) empty

View Answer

Answer: c [Reason:] If the stack flag is set, and condition code bit C1=0, then the stack has underflown.

3. The bits that affect the result of arithmetic operations like ADD, SUB, MUL, DIV are
a) condition code bits
b) rounding control bits
c) masking bits
d) precision control bits

View Answer

Answer: d [Reason:] The precision control bits affect ADD, SUB, MUL, DIV and SQRT results.

4. The precision is decided by the
a) opcode
b) extended precision format
c) opcode or extended precision format
d) none of the mentioned

View Answer

Answer: c [Reason:] For other than the arithmetic instructions (like ADD, SUB, MUL, DIV and SQRT), the precision is decided by opcode or extended precision format.

5. If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287

View Answer

Answer: c [Reason:] If Numeric Processor Write (NPWR) active-low input pin is activated, then it enables a data transfer from 80286 to 80287.

6. If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from
a) memory to processor
b) 80287 to 80286
c) 80286 to 80287
d) 8086 to 80287

View Answer

Answer: b [Reason:] If Numeric Processor Read (NPRD) active-low input pin is activated, then it enables a data transfer from 80287 to 80286.

7. Which of the input line(s) indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction?
a) NPWR (active low) and NPRD (active low)
b) NPS1 and NPS2 (active low)
c) NPS1 (active low) and NPS2
d) CMD0 and CMD1

View Answer

Answer: c [Reason:] The Numeric Processor select input lines, NPS1 (active low) and NPS2, indicate that the CPU is performing an escape operation, and enables 80287 to execute the next instruction.

8. For which pin of 80286 is the active low pin, BUSY of 80287, connected?
a) ERROR (active low)
b) BUSY (active low)
c) HLDA
d) TEST (active low)

View Answer

Answer: d [Reason:] The BUSY (active low) is connected to the TEST (active low) pin of 80286.

9. If Clock Mode (CM) input pin is held low, then the CLK input is divided by
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] If Clock Mode (CM) input pin is held high, then the CLK input is directly used for deriving the internal timings. Else, it is divided by 2.

10. Which of the following pin is not involved in the interface of 80287 with 80286?
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1

View Answer

Answer: c [Reason:] The 10 pins, PEREQ, PEACK#, BUSY#, ERROR#, NPRD(active low)#, NPWR(active low)#, NPS1(active low)#, NPS2#, CMD0 and CMD1.

11. The PEACK (active low) when activated, the pin that goes into deactivation is
a) PEREQ
b) ERROR#
c) RESET
d) CMD0 and CMD1

View Answer

Answer: a [Reason:] When the data transfer is over, the CPU activates PEACK (active low)# pin, which results in deactivating the PEREQ pin by 80287.

Interview MCQ Set 3

1. In the data type, packed byte, the number of bytes that can be packed into one 64-bit quantity is
a) 2
b) 4
c) 8
d) 16

View Answer

Answer: c [Reason:] In packed byte data type, eight bytes can be packed into one 64-bit quantity.

2. Four words can be packed into 64-bit by using the data type,
a) unpacked word
b) packed word
c) packed doubled word
d) one quad word

View Answer

Answer: b [Reason:] By using the packed word data type, four words can be packed into 64-bits.

3. The number of double words that can be packed into 64-bit register using packed double word is
a) 2
b) 4
c) 6
d) 8

View Answer

Answer: a [Reason:] Using packed double word, two double words can be packed into 64-bit.

4. The data type, “one quad word” packs __________ into 64-bit.
a) two 32-bit quantities
b) four 16-bit words
c) one 32-bit and two 16-bit quantities
d) one single 64-bit quantity

View Answer

Answer: d [Reason:] The data type, “one quad word” packs one single 64-bit quantity into 64-bit register.

5. If the result of an operation is overflowed(exceeded than 16 bits) or underflowed then, only the lower 16-bits of the result are stored in the register and this effect is known as
a) overflow/underflow effect
b) wrap-around effect
c) exceeding memory effect
d) none

View Answer

Answer: b [Reason:] If the result of an operation is overflowed (exceeded than 16 bits) or underflowed then, only the lower 16-bits of the result are stored in the register, and this effect is known as wrap-around effect.

6. In a multitasking operating system environment, each task should return to its own processor state which is
a) contents of integer registers
b) contents of floating point registers
c) contents of MMX registers
d) all of the mentioned

View Answer

Answer: d [Reason:] In a multitasking operating system environment, each task should return to its own processor state, which should be saved when the task switching occurs. The processor state here means the contents of the registers, both integer and floating point or MMX register.

7. Which of the following exception generated by MMX is the same type of memory access exception as the X86 instructions?
a) page fault
b) segment not present
c) limit violation
d) all of the mentioned

View Answer

Answer: d [Reason:] The MMX instruction set generates the same type of memory access exception as the X86 instructions namely; page fault, segment not present and limit violation.

8. When an MMX instruction is getting executed, the floating-point tag word is marked
a) 11
b) 10
c) 00
d) 01

View Answer

Answer: c [Reason:] When an MMX instruction is getting executed, the floating-point tag word is marked valid i.e. 00.

9. In a preemptive multitasking O.S., the saving and restoring of FP and MMX states are performed by
a) Control unit
b) O.S.
c) MMX instructions
d) MMX registers

View Answer

Answer: b [Reason:] In a preemptive multitasking O.S., the application does not know when it is preemptied. It is the job of the O.S. to save and restore the FP and MMX states, when performing a context switch. Thus the user need not save or restore the state.

10. The instruction of MMX that is essential when a floating-point routine calls an MMX routine or viceversa is
a) MOV
b) PADD
c) EMMS
d) None of the mentioned

View Answer

Answer: c [Reason:] The EMMS instruction is imperative when a floating point routine calls an MMX routine or vice-versa. If we do not use EMMS at the end of MMX routine, subsequent floating-point instructions will produce erratic results.

11. Pentium III is used in computers which run on the operating system of
a) windows NT
b) windows 98
c) unix
d) all of the mentioned

View Answer

Answer: d [Reason:] Pentium III is the best option to use in computers from high performance desktop to workstations and servers, running on operating systems like Windows NT, Windows 98 and UNIX.

12. The architecture of CPU of Pentium III is suitable for
a) multimedia
b) image processing
c) speech processing
d) all of the mentioned

View Answer

Answer: d [Reason:] The architecture of CPU of Pentium III is suitable for applications like imaging, image processing, speech processing, multimedia and internet applications.

13. The Pentium III has the operating frequencies as
a) 300MHz,350MHz,400MHz
b) 400MHz,450MHz,500MHz
c) 350MHz,400MHz,450MHz
d) 450MHz,500MHz,550MHz

View Answer

Answer: d [Reason:] The Pentium III has three versions operating at frequencies, 450MHz, 500MHz and 550MHz, which are all commercially available.

14. The Pentium III consists of
a) dual independent bus architecture
b) 512 Kbyte cache
c) eight 64-wide Intel MMX registers
d) all of the mentioned

View Answer

Answer: d [Reason:] The Pentium III has dual independent bus architecture that increases the bandwidth. It has a 512 Kbyte unified, non-blocking level2 cache and eight 64-wide Intel MMX registers.

Interview MCQ Set 4

1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned

View Answer

Answer: c [Reason:] The salient feature of Pentium is its superscalar, superpipelined architecture.

2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6

View Answer

Answer: b [Reason:] The Pentium has two integer pipelines, U and V, where each one is a 4-stage pipeline.

3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned

View Answer

Answer: b [Reason:] The Pentium has two separate caches. They are data cache and instruction cache.

4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned

View Answer

Answer: c [Reason:] The Pentium has two integer pipelines, U and V, where each one is a 4-stage pipeline. This enhances the speed of integer arithmetic of Pentium to a large extent.

5. For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned

View Answer

Answer: b [Reason:] For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of multiple instruction issue.

6. Which of the following is a class of architecture of MII (multiple instruction issue)?
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture

View Answer

Answer: d [Reason:] The MII architecture may again be classified into two categories: 1. Very long instruction word architecture 2. Superscalar architecture.

7. The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture

View Answer

Answer: c [Reason:] In VLIW processors, the compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group, and issues them in parallel for execution.

8. The architecture in which the hardware decides which instructions are to be issued concurrently at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture

View Answer

Answer: d [Reason:] In superscalar architecture, the hardware decides which instructions are to be issued concurrently at run time.

9. The CPU has to wait till the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned

View Answer

Answer: b [Reason:] In conditional branch, the CPU has to wait till the execution stage to determine whether the condition is met or not. When the condition satisfies, a branch is to be taken.

10. The memory device that holds branch target addresses for previously executed branches is
a) Tristate buffer
b) RAM
c) ROM
d) Branch target buffer

View Answer

Answer: d [Reason:] The branch target buffer in Pentium CPU holds branch target addresses for previously executed branches.

11. The branch target buffer is
a) four-way set-associative memory
b) has branch instruction address
c) has destination address
d) all of the mentioned

View Answer

Answer: d [Reason:] The branch target buffer is a four-way set-associative memory. Whenever a branch is taken, the CPU enters the branch instruction address, and also the destination address in the branch target buffer.

Interview MCQ Set 5

1. In ‘Rotate source, count’ instructions, if the CF is equal to MSB of operand (source) then
a) TF is cleared
b) OF is cleared
c) TF is set
d) OF is set

View Answer

Answer: b [Reason:] If CF is equal to MSB of operand (source), the overflow flag is cleared, otherwise, it is set to 1.

2. The instruction that affects the flags is
a) IMUL
b) INSW
c) INSB
d) POP*A

View Answer

Answer: a [Reason:] No flags are affected by the instructions, INSW, INSB and POP*A.

3. A general protection exception is generated, if the value of
a) CPL is equal to that of IOPL
b) CPL is less than that of IOPL
c) CPL is greater than that of IOPL
d) None of the mentioned

View Answer

Answer: c [Reason:] When the value of CPL is greater than that of IOPL, a general protection exception is generated.

4. While executing the instruction, OUTSW, the SI is incremented by
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] The SI is automatically incremented by 1 for byte (OUTSB) and 2 for word (OUTSW) operations.

5. The instruction that is used to exit the procedure is
a) QUIT
b) STOP
c) LEAVE
d) EXIT

View Answer

Answer: c [Reason:] The instruction, LEAVE, is generally used with high level languages, to exit a procedure.

6. The instruction that determines the number of bytes, to be copied into the new stack frame, from the previous stack is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE

View Answer

Answer: a [Reason:] The ENTER instruction prepares a stack structure for parameters of a procedure to be executed further. This instruction determines the number of bytes to be copied, into the new stack frame, from the previous stack.

7. The instruction that is used to check whether a signed array offset is within the limit, defined for it by the starting and ending index is
a) ENTER
b) BOUND
c) CLTS
d) LEAVE

View Answer

Answer: b [Reason:] The BOUND instruction is used to check whether a signed array offset is within the limit defined for it, by the starting and ending index.

8. The CLTS (Clear Task Switch Flag) instruction records every execution of WAIT and ESC and is trapped if the flag(s)
a) PE (Protection Enable) and TS (task switch) flags are set
b) Emulate Processor extension flag is set
c) MP flag and task switched flag are set
d) PE and MP flag are set

View Answer

Answer: c [Reason:] The CLTS (Clear Task Switch Flag) instruction records every execution of WAIT and ESC, and is trapped, if the MP flag and task switched flag are set.

9. The instruction that determines whether the segment pointed to, by a 16-bit register, can be accessed from the current privilege level is
a) RPL
b) CPL
c) ARPL
d) VERR

View Answer

Answer: d [Reason:] The VERR/VERW instructions determine whether the segment pointed to, by a 16-bit register, can be accessed from the current privilege level.

10. The instruction that loads 6 bytes from a memory block, pointed to by the effective address of the operand, into global descriptor table register is
a) LLDT
b) SGDT
c) LGDT
d) None of the mentioned

View Answer

Answer: c [Reason:] The LGDT (load global descriptor table register) loads 6 bytes from a memory block, pointed to by the effective address of the operand, into global descriptor table register.

11. In LGDT instruction, while loading 6 bytes, the first word is loaded into the field of
a) LIMIT field
b) BASE field
c) Either LIMIT or BASE field
d) None of the mentioned

View Answer

Answer: a [Reason:] While loading the 6 bytes, the first word is loaded into the LIMIT field of the descriptor table register. The next three bytes are loaded into the BASE field of the register, and the remaining byte is ignored.