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Interview MCQ Set 1

1. Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned

View Answer

Answer: d [Reason:] In the request register, each bit is set or reset under program control or is cleared upon generation of a TC or an external EOP.

2. The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register

View Answer

Answer: b [Reason:] The temporary register holds the data during memory to memory data transfers. After the completion of the transfer operation, the last word transferred remains in the temporary register, till it is cleared by a reset operation.

3. The register that keeps track of all the DMA channel pending requests, and status of their terminal counts is
a) mask register
b) request register
c) status register
d) count register

View Answer

Answer: c [Reason:] The status register keeps track of all the DMA channel pending requests, and status of their terminal counts. These are cleared upon reset.

4. The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET

View Answer

Answer: d [Reason:] A high on the reset pin clears the command, status, request and temporary registers, and also clears the internal first/last flipflop.

5. The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3

View Answer

Answer: a [Reason:] DREQ0 has the highest priority while DREQ3 has the lowest one. The priorities of the DREQ lines is programmable.

6. When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned

View Answer

Answer: c [Reason:] If 8237 is in idle state, then CPU may program it in this state.

7. To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned

View Answer

Answer: c [Reason:] A memory to memory transfer is a two cycle operation, and requires a read from and write-to memory cycle, to complete each DMA transfer.

8. In demand transfer mode of 8237, the device stops data transfer when
a) a TC (terminal count) is reached
b) an external EOP (active low) is detected
c) the DREQ signal goes inactive
d) all of the mentioned

View Answer

Answer: d [Reason:] In demand transfer mode, the device continues transfers till a TC is reached or an external EOP is detected or the DREQ signal goes inactive.

9. The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode

View Answer

Answer: b [Reason:] In single mode, the device transfers only one byte per request. For each transfer, the DREQ must be active until the DACK is activated.

10. The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode

View Answer

Answer: c [Reason:] To perform the transfer of a block of data from one set of memory address to another one, this transfer mode is used.

11. Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned

View Answer

Answer: b [Reason:] Using master clear command, all the internal registers of 8237 are cleared, while all the bits of the mask register are set.

Interview MCQ Set 2

1. If the most significant bit of relative address byte is 1, then the short jump instruction is
a) forward jump
b) back jump
c) either forward or back jump
d) none

View Answer

Answer: b [Reason:] If the most significant bit of relative address byte is 1, then the short jump instruction is back jump, else it is considered as forward jump.

2. The first byte of an absolute jump instruction consists of
a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address

View Answer

Answer: d [Reason:] The first byte of an absolute jump instruction consists of 5 LSBs of opcode and 3 MSBs of 11-bit address. The next byte carries the least significant 8 bits of the 11-bit address.

3. The third byte of the long jump instruction is
a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine

View Answer

Answer: c [Reason:] The third byte of the long jump instruction is higher byte of jump location or subroutine.

4. The absolute jump instruction is intended mainly for a jump within a memory space of
a) 2 bytes
b) 2 Kbytes
c) 2 Mbytes
d) none

View Answer

Answer: b [Reason:] The absolute jump instruction is intended mainly for a jump within a memory space of 2 Kbytes.

5. The LJMP instruction is very useful in programming in the external code memory space of
a) 32 MB
b) 64 MB
c) 32 KB
d) 64 KB

View Answer

Answer: d [Reason:] The LJMP instruction is very useful in programming in the external code memory space of 64 KB.

6. Which of the following is not an unconditional control transfer instruction?
a) JMP
b) RET
c) JNC
d) CALL

View Answer

Answer: c [Reason:] The instructions, JMP, RET, RETI, CALL are the unconditional control transfer instructions.

7. The conditional control transfer instructions use
a) status flags
b) bits of bit addressable RAM
c) SFRs termed bit
d) all of the mentioned

View Answer

Answer: d [Reason:] The conditional control transfer instructions use status flags or bits of bit addressable RAM or SFRs termed bit.

8. Which of the following is not a conditional control transfer instruction?
a) JC
b) JBC
c) JNC
d) NONE

View Answer

Answer: d [Reason:] The instructions, JC, JBC, JNC, JB and JNB are the conditional control transfer instructions.

9. The mnemonic used to perform a subtraction of source with an 8-bit data and jumps to specified relative address if subtraction is non-zero is
a) DJNZ
b) CJNE
c) JZ
d) JNC

View Answer

Answer: b [Reason:] The CJNE instruction perform a subtraction of source with an 8-bit data and jumps to specified relative address only if the result of the subtraction is non-zero, else continues to the next instruction.

10. The mnemonic, JNB is used to jump to the specified relative address only if
a) specified bit=1
b) specified bit=0
c) specified bit is non-recursive
d) none

View Answer

Answer: a [Reason:] The mnemonic, JNB is used to jump to the specified relative address only if specified bit=1, else continues to the next instruction.

11. The type of operand that is not allowed to use in boolean instructions of 8051 is
a) direct register operands
b) indirect register operands
c) immediate bit
d) none

View Answer

Answer: c [Reason:] In boolean instructions, immediate bit is not allowed as an operand.

12. In boolean instructions, the flag that is the only allowed destination operand for two operand instructions is
a) overflow flag
b) underflow flag
c) auxiliary flag
d) carry flag

View Answer

Answer: d [Reason:] Carry flag(C) is the only allowed destination operand for two operand instructions in boolean instructions.

Interview MCQ Set 3

1. If EA(active low) signal =1, then the execution starts from
a) internal EPROM
b) flash RAM
c) internal EPROM or flash RAM
d) none

View Answer

Answer: c [Reason:] If EA(active low) signal =1, then the execution starts from an internal EPROM or flash RAM address 000H, can continue upto FFFH address and then for higher addresses it will go into external memory.

2. The pin that is grounded for interfacing external EPROM is
a) EA(active low)
b) PSEN(active low)
c) OE(active low)
d) All of the mentioned

View Answer

Answer: a [Reason:] The EA(active low) pin is grounded for interfacing external EPROM. The PSEN(active low) is used for interfacing EPROM i.e. it acts as an OE(active low) input to EPROM.

3. The step that is involved in the procedure of memory interfacing with 8051 is
a) data bus is connected to data lines of memory chips
b) PSEN(active low) is connected to OE(active low) of EPROM chips
c) writing address map of memory chip in bit form
d) all of the mentioned

View Answer

Answer: d [Reason:] The procedure of memory interfacing with 8051 includes, data bus connection to data lines of memory chips, PSEN(active low) connected to OE(active low) of EPROM chips and writing address map of memory chip in bit form.

4. The device that is used for deriving chip select signals is
a) Logic gates
b) Multiplexers
c) PLAs and EPROMs
d) All of the mentioned

View Answer

Answer: d [Reason:] The logic gates and multiplexers are most commonly used for deriving chip select signals. The advanced circuits like PLAs and EPROMs are also used for deriving chip select signals.

5. For deriving chip selects of isolated memory or IO devices, the gates that are traditionally used are
a) NOR and NAND
b) NAND and NOT
c) NOT and NOR
d) AND, OR and NOT

View Answer

Answer: b [Reason:] For deriving chip selects of isolated memory or IO devices, the NAND and NOT gates are traditionally used.

6. The current that is required for a LED for an appropriate glow is
a) 6-8 mA
b) 4-6 mA
c) 8-10 mA
d) 10-12 mA

View Answer

Answer: c [Reason:] For appropriate glow, a LED typically requires 8-10 mA with around 1.6 Volts.

7. The maximum current that can be sinked totally by all the ports of 8051 is
a) 61 mA
b) 81 mA
c) 91 mA
d) 71 mA

View Answer

Answer: d [Reason:] All the ports together (4 ports) should not be made to sink more than 71 mA.

8. The number of LEDs that can be connected to a port of 8051, if all are expected to glow simultaneously is
a) 6
b) 8
c) 10
d) 12

View Answer

Answer: b [Reason:] If 8 LEDs are connected to a port of 8051, and if all are expected to glow simultaneously, the total current sinked by the 8051 port will be 8×8=64 mA (since min voltage for an LED to glow=8 mA) which is less than the maximum 71 mA.

9. Which is true in interfacing 7 segment code display?
a) transmitted by second port
b) display is selected by third port
c) display is selected by second port
d) none of the mentioned

View Answer

Answer: c [Reason:] The 7-segment code of a digit is transmitted by the first port and the display is selected by second port. As soon as the display is selected by the second port, the digit starts glowing on that display position.

10. After display is selected by second port, then the digit (LED) glows for a duration of
a) 5 msec
b) 10 msec
c) 2 msec
d) 6 msec

View Answer

Answer: a [Reason:] The unit(LED) glows for a duration of 5 msec.

11. The number of scans of the complete 8-digit display that can be carried out in one second is
a) 15
b) 25
c) 35
d) 55

View Answer

Answer: b [Reason:] Starting from either right most or left most digit, every digit glows for 5 msec one by one. Thus one scan of the 8 digit display requires 40 msec. Thus in one second, 25 scans of the complete 8-digit display can be carried out.

12. To convert its current output into voltage, the DAC 0808 is connected with
a) Transistor(BJT) externally
b) FET externally
c) OPAMP externally
d) OPAMP internally

View Answer

Answer: c [Reason:] the DAC 0808 is connected with OPAMP externally, to convert its current output into voltage.

Interview MCQ Set 4

1. If the logical processors want to execute complex IA-32 instructions simultaneously then the number of microcode instruction pointers required is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] If both the logical processors want to execute complex IA-32 instructions simultaneously then two microcode instruction pointers are required, which will access the microcode ROM.

2. Which of the following is a type of branch prediction?
a) static prediction
b) dynamic prediction
c) static and dynamic prediction
d) none

View Answer

Answer: c [Reason:] There are two types of branch prediction namely static prediction and dynamic prediction.

3. The prediction that is based on a statistical assumption that the majority of backward branches occur in repetitive loops is
a) static prediction
b) dynamic prediction
c) branch prediction
d) none

View Answer

Answer: a [Reason:] The static prediction is based on a statistical assumption that the majority of backward branches occur in the context of repetitive loops.

4. The advantage of static prediction is
a) simple and fast
b) does not require table lookups or calculations
c) performs without much degradation
d) all of the mentioned

View Answer

Answer: d [Reason:] The static prediction is simple and fast. It does not require table lookups or calculations. In case if program contains a number of loops, static prediction performs without much degradation.

5. The dynamic branch prediction algorithms uses
a) Branch History Table (BHT)
b) Branch Target Buffer (BTB)
c) Branch History Table and Branch Target Buffer
d) None

View Answer

Answer: c [Reason:] The dynamic branch prediction algorithms uses two types of tables, namely Branch History Table (BHT) and Branch Target Buffer (BTB).

6. The unit that preserves the history of each conditional branch is
a) Branch Target Buffer (BTB)
b) Branch History Table (BHT)
c) Static prediction
d) Dynamic prediction

View Answer

Answer: b [Reason:] The Branch History Table (BHT) preserves the history of each conditional branch that the speculative branch prediction unit encounters during the last several cycles.

7. The BHT keeps a record that indicates the likelihood of the branches grouped as
a) strongly taken
b) taken
c) not taken
d) all of the mentioned

View Answer

Answer: e [Reason:] The BHT keeps a record that indicates the likelihood that the branch will be taken based on its past history. The branches may be grouped as ‘strongly taken’, ‘taken’, ‘not taken’ and ‘strongly not taken’.

8. Each logical processor has
a) one 64-byte streaming buffer
b) one 32-byte streaming buffer
c) two 64-byte streaming buffers
d) two 32-byte streaming buffers

View Answer

Answer: c [Reason:] Each logic processor has its own set of two 64-byte streaming buffers, which store the instruction bytes and subsequently they are dispatched to the instruction decode stage.

9. If there is a trace cache miss, then the instruction bytes are required to be fetched from the
a) instruction decoder
b) Level2 cache
c) execution module
d) none of the mentioned

View Answer

Answer: b [Reason:] If there is a trace cache miss, then the instruction bytes are required to be fetched from the Level2 cache.

10. The Instruction Translation Lookaside Buffer(ITLB) is present in
a) trace cache
b) instruction decoder
c) logical processors
d) all of the mentioned

View Answer

Answer: c [Reason:] Since there are two logical processors, there are two ITLBs. Thus each logical processor has its own ITLB and its own instruction pointer to track the progress of instruction fetch for each of them.

Interview MCQ Set 5

1. DAC (Digital to Analog Converter) finds application in
a) digitally controlled gains
b) motor speed controls
c) programmable gain amplifiers
d) all of the mentioned

View Answer

Answer: d [Reason:] DAC is used in digitally controlled gains, motor speed controls and programmable gain amplifiers.

2. To save the DAC from negative transients the device connected between OUT1 and OUT2 of AD 7523 is
a) p-n junction diode
b) Zener
c) FET
d) BJT (Bipolar Junction transistor)

View Answer

Answer: b [Reason:] Zener is connected between OUT1 and OUT2 pins of AD7523 to save from negative transients.

3. An operational amplifier connected to the output of AD 7523 is used
a) to convert current output to output voltage
b) to provide additional driving capability
c) as current-to-voltage converter
d) all of the mentioned

View Answer

Answer: d [Reason:] An operational amplifier is used as a current-to-voltage converter to convert current output to output voltage and also provides additional driving capability to the DAC.

4. The DAC 0800 has a settling time of
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 microseconds

View Answer

Answer: a [Reason:] DAC 0800 has a settling time of 100 milliseconds.

5. The device that is used to obtain an accurate position control of rotating shafts in terms of steps is
a) DC motor
b) AC motor
c) Stepper motor
d) Servo motor

View Answer

Answer: c [Reason:] Stepper motor employs rotation of its shaft in terms of steps, rather than continuous rotation as in case of AC or DC motors.

6. The internal schematic of a typical stepper motor has
a) 1 winding
b) 2 windings
c) 3 windings
d) 4 windings

View Answer

Answer: d [Reason:] The internal schematic of a typical stepper motor has 4 windings.

7. The number of pulses required for one complete rotation of the shaft of the stepper motor is equal to the
a) number of internal teeth on a rotor
b) number of internal teeth on a stator
c) number of internal teeth on a rotor and stator
d) number of external teeth on a stator

View Answer

Answer: a [Reason:] The number of pulses required for one complete rotation of the shaft of the stepper motor is equal to the number of internal teeth on its rotor.

8. A simple scheme for rotating the shaft of a stepper motor is called
a) rotating scheme
b) shaft scheme
c) wave scheme
d) none

View Answer

Answer: c [Reason:] In this scheme, the windings are applied with the required voltage pulses, in a cyclic fashion.

9. The firing angles of thyristors are controlled by
a) pulse generating circuits
b) relaxation oscillators
c) microprocessor
d) all of the mentioned

View Answer

Answer: d [Reason:] In early days, the firing angles were controlled by pulse generating circuits like relaxation oscillators and now, they are accurately fired using a microprocessor.

10. The Isolation transformers are generally used for
a) protecting low power circuit
b) isolation
c) protecting low power circuit and isolation
d) none

View Answer

Answer: c [Reason:] Any switching component of a high power circuit may be sufficient to damage the microprocessor system. So, to protect the low power circuit isolation transformers are used. They are also used if isolation is necessary.