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Interview MCQ Set 1

1. The MMX instructions support only
a) character data type
b) float data type
c) integer data type
d) string data type

View Answer

Answer: c [Reason:] The MMX instructions support only integer data type.

2. For single precision floating point numbers, the SSE instructions are
a) MMX instructions
b) SIMD instructions
c) Floating point executions
d) None

View Answer

Answer: b [Reason:] The SSE instructions are SIMD(Single Instruction Multiple Data Stream) instructions for single precision floating point numbers.

3. The feature of SSE among the following is
a) operate on four 32-bit floating points
b) register size is of 128 bits
c) no switching from one mode to other
d) all of the mentioned

View Answer

Answer: d [Reason:] The features of SSE(Streaming SIMD extensions) are 1. SSE instructions are SIMD instructions for single precision floating point numbers. 2. They operate on four 32-bit floating points. 3. The register size is of 128 bits 4. No necessity to switch from one mode to other.

4. The new instructions that are added in SSE for floating point operations are of
a) 72
b) 50
c) 25
d) 8

View Answer

Answer: b [Reason:] The new instructions that are added in SSE for floating point operations are 50.

5. The SSE instructions can operate on
a) packed data
b) unpacked data
c) dynamic data
d) all of the mentioned

View Answer

Answer: a [Reason:] The SSE instructions can operate on packed data or scalar data.

6. Which of the following group is not of SSE instructions?
a) jump or branch group of instruction
b) logic and comparison group of instruction
c) shuffle instructions
d) all of the mentioned

View Answer

Answer: d [Reason:] The SSE instructions can be grouped to many types. Some of them are 1. Data transfer instructions 2. Arithmetic, logic and comparison group of instruction 3. shuffle instructions 4. Cacheability instructions.

7. Which of the following is true about SSE2 instructions in Pentium III and Pentium 4?
a) SSE increases the accuracy of double precision floating point operations
b) SSE supports new formats of packed data
c) SSE increases the speed of manipulation of SIMD integer operations
d) All of the mentioned

View Answer

Answer: d [Reason:] The SSE new instruction set increases the accuracy of double precision floating point operations, supports new formats of packed data.

8. The data type that the SSE2 instructions doesnot support is
a) single precision floating points
b) double precision floating points
c) single and double precision floating points
d) none of the mentioned

View Answer

Answer: d [Reason:] The SSE2 instructions support new data types such as double precision floating points along with single precision floating points.

9. The additional instructions of SSE3 over SSE2 contains
a) video encoding
b) complex arithmetic operation
c) thread synchronisation
d) all of the mentioned

View Answer

Answer: d [Reason:] The SSE3 contains 13 additional SIMD instructions over SSE2. These instructions comprise five types. i. floating point to integer conversion ii. complex arithmetic operation iii. video encoding iv. SIMD floating point operations using array of structures format v. thread synchronisation.

10. The unit that may acts as interface between the Front end and the Out of order execution engine in the pipeline flow is
a) micro-op queue
b) micro-op stack
c) micro-ops
d) none

View Answer

Answer: a [Reason:] The micro-op queue acts as interface between the Front end and the Out of order execution engine in the pipeline flow.

11. The verification of the logic using formal mathematical tools is called
a) arithmetic verification
b) formal verification
c) mathematical verification
d) logical verification

View Answer

Answer: b [Reason:] The verification of the logic using formal mathematical tools is called formal verification.

12. The formal verification is important for
a) developing the tools
b) developing the methodologies
c) to detect the bugs in design
d) all of the mentioned

View Answer

Answer: d [Reason:] The formal verification is important to develop the tools and methodologies to handle a large number of proofs using which it will be possible to detect the bugs in the design.

13. By using the techniques of formal verification, one can detect the logical bugs of
a) more than 50
b) less than 50
c) more than 100
d) less than 100

View Answer

Answer: c [Reason:] By using the techniques of formal verification, one can detect more than 100 logical bugs.

14. The modern processors are designed to achieve
a) high speed
b) operate at low operating voltage
c) uses cooling technology
d) all of the mentioned

View Answer

Answer: d [Reason:] The modern processors are designed to operate at a very high speed and even with the lower operating voltages, the power consumption is high enough to require expensive cooling technology.

Interview MCQ Set 2

1. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3

View Answer

Answer: c [Reason:] This instruction adds 1 to the contents of the operand and so increments by 1.

2. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC

View Answer

Answer: d [Reason:] The DEC instruction decrements the contents of specified register/memory location by 1.

3. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned

View Answer

Answer: c [Reason:] The SBB instruction subtracts the source operand and the borrow flag from the destination operand.

4. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag

View Answer

Answer: b [Reason:] If borrow exists in the subtraction operation performed then carry flag is set.

5. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned

View Answer

Answer: d [Reason:] The source operand is the element which is data or data stored memory location on which operation is performed.

6. In general, the destination operand of an instructon can be
a) memory location
b) register
c) immediate data
d) memory location and register

View Answer

Answer: d [Reason:] Since the destination should be able to store the data, immediate data cannot be considered as destination operand.

7. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication

View Answer

Answer: b [Reason:] For comparison, the instruction CMP subtracts source operand from destination operand.

8. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where

View Answer

Answer: d [Reason:] The result of subtraction operation is not stored anywhere during comparison.

9. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned

View Answer

Answer: e [Reason:] All the ASCII adjust instructions give result in unpacked decimal form and so are called as “Unpacked BCD arithmetic instructions”.

10. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC

View Answer

Answer: c [Reason:] AAA is a mnemonic.It doesn’t has either source or destination operand.

11. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD

View Answer

Answer: d [Reason:] The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits.

12. The expansion of DAA is
a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary

View Answer

Answer: c [Reason:] This instruction performs conversion operation.

13. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS

View Answer

Answer: a [Reason:] In this conversion, the result has to be only in AL.

14. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left

View Answer

Answer: b [Reason:] ROR stands for Rotate Right without carry.so, the instruction rotates right.

Interview MCQ Set 3

1. Which of the following is a supporting chip of 80286?
a) interrupt controller
b) clock generator
c) bus controller
d) all of the mentioned

View Answer

Answer: d [Reason:] The interrupt controller 8259A, clock generator 82C284, and bus controller 82C288, are the unavoidable members of the family, of supporting chips of 80286.

2. In minimum mode, the function of 80286 is
a) data transfers to/from memory or I/O
b) controls the data transfer of 80287
c) controls the instruction execution of 80287
d) all of the mentioned

View Answer

Answer: d [Reason:] In minimum mode, the 80286 carries out all the data transfers to/from memory or I/O, controls the data transfer, and instruction execution of 80287.

3. The signal that is applied to the decoding logic, to differentiate between interrupt, code fetch and data bus cycles is
a) COD
b) INTA (active low)
c) M/IO (active low)
d) All of the mentioned

View Answer

Answer: d [Reason:] The COD, INTA (active low), M/IO (active low) signals are applied to the decoding logic, to differentiate between interrupt, I/O, code fetch, and data bus cycles.

4. By adding which of the following, the minimum mode of 80286 gives the multibus interface of 80286?
a) bus controller
b) bus arbiter
c) interrupt controller
d) all of the mentioned

View Answer

Answer: b [Reason:] The addition of single chip 82C289 known as bus arbiter, to the configuration of 80286 minimum mode, gives the multibus structure of 80286.

5. The number of bus controllers that are used for interfacing of memory and I/O devices is
a) 1
b) 2
c) 3
d) none of the mentioned

View Answer

Answer: b [Reason:] The interfacing of memory and I/O devices, uses two 82288 bus controllers, one each for local, and system bus.

6. If the 80286 need to use system bus, then the signal that is to be active is
a) SRDY
b) SRDYEN
c) ARDYEN
d) ARDY

View Answer

Answer: c [Reason:] The ARDYEN pin is to be activated, if the 80286 is to use system bus. The SRDYEN pin is to be grounded.

7. If MBYTES input is high, then the pin serves as
a) AEN
b) CEN
c) AEN and CEN
d) None of the mentioned

View Answer

Answer: a [Reason:] The MBYTES input selects the function of AEN/CEN pin. If MBYTES is high, the pin serves as AEN, else it serves as CEN. The CEN pin is used for selecting one of the available 82288s.

8. Latches are used in 80286 to
a) demultiplex the address and data lines
b) latch the address signals
c) decode the select signals
d) latch the address and decode the select signals

View Answer

Answer: d [Reason:] The address and data lines are not multiplexed, hence no latches are required in 80286 system. Rather the addresses of the next bus cycle are displayed in advance, hence the latches are required for latching the address, and decode the signals.

9. The I/O port addresses, that are not used, while designing practical systems around 80286 are
a) 0000H to 00FFH
b) 00FFH to FFFFH
c) 00F8H to 00FFH
d) 0000H to FFFFH

View Answer

Answer: c [Reason:] The I/O port addresses 00F8H to 00FFH are reserved by Intel, hence these should not be used, while designing practical systems around 80286.

Interview MCQ Set 4

1. The method of defining the interrupt service routine for software is
a) same as that of hardware
b) difficult than hardware
c) easier than software
d) none of the mentioned

View Answer

Answer: a [Reason:] For both software and hardware, the method of defining the interrupt service routine is same.

2. While programming for any type of interrupt, the interrupt vector table is set
a) externally
b) through a program
c) either externally or through the program
d) externally and through the program

View Answer

Answer: c [Reason:] The programmer must, either externally or through the program, set the interrupt vector table for that type preferably with the CS and IP addresses of the interrupt service routine.

3. To execute a program one should
a) assemble the program
b) link the program
c) apply external pulse
d) all of the mentioned

View Answer

Answer: d [Reason:] To execute a program, first assemble it, link it and then execute it. After execution, a new file RESULT is created in the directory. Then external pulse is applied to IRQ2 pin, and this will again cause the execution of ISR into the file.

4. Procedures are also known as
a) macros
b) segment
c) subroutines
d) none

View Answer

Answer: c [Reason:] Procedures are also known as subroutines.

5. Procedures, for their execution, require
a) input data
b) output data
c) constants
d) input data or constants

View Answer

Answer: d [Reason:] Procedures require input data or constants for their execution. Their data or constants may be passed to the subroutine by the main program.

6. The technique that is used to pass the data or parameter to procedures in assembly language program is by using
a) global declared variable
b) registers
c) stack
d) all of the mentioned

View Answer

Answer: d [Reason:] The techniques that are used to pass the data or parameter to procedures are by using global declared variable, registers of CPU, memory locations, stack, PUBLIC & EXTRN.

7. If a procedure is interactive, then
a) it accepts inputs directly from input devices
b) it uses global declared variable technique
c) it uses stack
d) it uses memory locations

View Answer

Answer: a [Reason:] If a procedure is interactive, then it accepts the inputs directly from input devices.

8. For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must be declared PUBLIC in the
a) subroutine
b) procedure
c) main routine
d) main routine and subroutine

View Answer

Answer: c [Reason:] For passing the parameters to procedures, it must be declared PUBLIC in the main routine and the same should be declared EXTRN in the procedure.

9. The technique to estimate the size of an executable program, before it is assembled and linked is
a) memory location technique
b) global variable technique
c) stack
d) none

View Answer

Answer: d [Reason:] There is no technique to estimate the size of an executable program, before it is assembled and linked.

10. To estimate the size of an executable program before it is assembled and linked, the programming methodology concerned is by writing
a) programs with more than one segment for data and code
b) programs with FAR subroutines each of size upto 64KB
c) programs with more than one segment for stack
d) all of the mentioned

View Answer

Answer: d [Reason:] By writing programs with more than one segment for data, code or stack or by writing programs with FAR subroutines each of size 64KB, the size of an executable program can be estimated.

Interview MCQ Set 5

1. The 32-bit control register, that is used to hold global machine status, independent of the executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned

View Answer

Answer: d [Reason:] The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine status, independent of the executed task.

2. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) All of the mentioned

View Answer

Answer: d [Reason:] The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.

3. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR

View Answer

Answer: a [Reason:] The GDTR and IDTR are known as system address registers.

4. Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned

View Answer

Answer: b [Reason:] The LDTR and TR are known as system segment registers.

5. The test register(s) that is provided by 80386 for page cacheing is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers

View Answer

Answer: c [Reason:] Two test registers are provided by 80386 for page cacheing, namely test control and test status registers.

6. Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7

View Answer

Answer: b [Reason:] Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.

7. The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3

View Answer

Answer: d [Reason:] The initial four registers, DR0-DR3 store four program controllable break point addresses.

8. The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned

View Answer

Answer: a [Reason:] The registers DR6 and DR7 respectively hold break point status and break point control information.

9. The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned

View Answer

Answer: b [Reason:] The IOPL flag bits indicate the privilege level of current IO operations.

10. The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers

View Answer

Answer: c [Reason:] The segment descriptor registers of 80386 are not available for programmers, rather, they are internally used to store the descriptor information.

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