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Interview MCQ Set 1

1. Asynchronous serial communication usually requires two wires for each direction plus a common ground.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] Asynchronous serial communication usually requires only a single wire for each direction plus a common ground.

2. In asynchronous mode of transmission, usually the data is sent along with the
a) the start bit
b) the stop bit
c) both of the mentioned
d) none of the mentioned

View Answer

Answer: c [Reason:] In asynchronous mode of transmission, both the start and the stop bits are present that are basically used for intimating the other terminal that whether the data had received correctly the other destination or not.

3. The _____ rate gives the frequency at which the bits are transmitted on the line.
a) bit rate
b) packet rate
c) baud rate
d) data rate

View Answer

Answer: c [Reason:] Baud rate is the rate which determines us the frequency at which the bits are transmitted on the line.

4. Baud rate is the reverse of the
a) baud time
b) baud period
c) bit time
d) bit period

View Answer

Answer: b [Reason:] Baud rate is the reverse of the baud period.

5. Clock is transmitted in the asynchronous communication?
a) yes
b) no
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] No clock is transmitted in the asynchronous communication, so the transmitter and the receiver are allowed to work independently at their own terminals.

6. A framing error occurs is the bit is
a) high
b) low
c) same
d) changed

View Answer

Answer: b [Reason:] Framing error occurs if the bit is low.

7. What is the non return to zero format?
a) the bits are either high or low and have no gaps between them
b) the bits are either high or low and have gaps between them
c) the bits are high and have gaps between them
d) the bits are low and have no gaps between them

View Answer

Answer: a [Reason:] Non-return to zero format represents a format in which the bits are either high or low and have no gaps between them.

8. LSB is sent first in case of the non return to zero format.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] In non-return to zero format, normally LSB is sent first.

9. Their are _______ clocks in the USCI_A.
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] Their are 3 clocks in the USCI_A. They are BRCLK, BITCLK and BITCLK16.

10. BITCLK16 is the
a) sampling clock in the undersampling mode
b) sampling clock in the oversampling mode
c) quantising clock in the undersampling mode
d) quantising clock in the oversampling mode

View Answer

Answer: b [Reason:] BITCLK16 is the sampling clock in the oversampling mode.

Interview MCQ Set 2

1. Is SPI a full duplex technique?
a) yes
b) no
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] Yes, SPI is a technique where a data can be transmitted/ received in both the directions.

2. The concept of SPI is based on
a) two counters
b) four flip flops
c) two shift registers
d) four steady state machines

View Answer

Answer: c [Reason:] The concept of the SPI is based on the two shift registers, one for the transmitter and the other is there for the receiver terminal.

3. Writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse is done when
a) CPHA is set
b) CPHA is reset
c) CPOL is set
d) CPOL is reset

View Answer

Answer: b [Reason:] When CPHA is reset to zero, then writing on the trailing edge of the clock pulse and reading on the leading edge of the clock pulse.

4. When CPOL=1 then,
a) clock idles high between transfers
b) clock idles low between transfers
c) bit idles high between transfers
d) bit ideals low between transfers

View Answer

Answer: a [Reason:] When CPOL=1, clock idles high between transfers.

5. Is CPKH and CPOL the same
a) yes
b) no
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] CPKL=CPOL and CPKH=(not CPHA).

6. SPI with the USI can be selected by
a) setting the USII2C bit in the register USICTL1
b) clearing the USII2C bit in the register USICTL1
c) setting the USIPE5–7 bits in USICTL0
d) clearing the USIPE5–7 bits in USICTL0

View Answer

Answer: b [Reason:] SPI with the USi can be selected by clearing the USII2C bit in the register USICTL1.

7. SCLK, SDO, and SDI are found___________on F20x3.
a) P1.0-2
b) P1.2-4
c) P1.4-6
d) P1.5-7

View Answer

Answer: d [Reason:] SCLK, SDO, and SDI are found at P1.5-7 on F20x3.

8. Transmission and reception are made at a time in SPI?
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] Transmission and reception occurs at a time in SPI. This means that a value is received only if the transmitter is active.

9. When the buffer is________ the low power mode is__________
a) empty, reset
b) having one byte, reset
c) full, reset
d) empty, two

View Answer

Answer: c [Reason:] When the buffer is full, the low power mode is cleared.

10. Falling edge of the SS pin denotes
a) end of the transfer
b) starts a new transfer
c) selects a new master
d) none of the mentioned

View Answer

Answer: b [Reason:] Falling edge of the SS pin denotes start of a new transfer over SPI.

Interview MCQ Set 3

1. The successive approximation converters have resolution of
a) 8-10 bits
b) 10-12 bits
c) 12-16 bits
d) 16-32 bits

View Answer

Answer: b [Reason:] The successive approximation converters have resolution of about 10-12 bits in it.

2. In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and set up the new voltage.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] In SAR based conversions, each bit typically requires one clock cycle (sometimes two) to make a comparison and set up the new voltage.

3. The main operations that are basically performed in a SAR ADC are?
a) logic to control the operation
b) some way of generating the voltages, for comparison
c) both of the mentioned
d) none of the mentioned

View Answer

Answer: c [Reason:] The main operations that are basically performed in a SAR ADC are the logic to control the operation and finding some way of generating the voltages, for comparison.

4. Usually a capacitor is inserted between an analog input and the ground because
a) it blocks the analog voltage
b) it suppresses the noise
c) it increases the gain
d) none of the mentioned

View Answer

Answer: b [Reason:] A capacitor in inserted between the analog input and the ground because it suppresses the noise.

5. ADC10 and ADC12 are
a) The converters
b) SAR modules available in the MSP430
c) Sigma delta modules available in the MSP430
d) Comparator modules available in the MSP430

View Answer

Answer: b [Reason:] ADC10 and ADC12 are the SAR modules available in the MSP430.

6. ADC10 needs external capacitors on its voltage reference.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] ADC12 needs external capacitors on its voltage reference as compared to the ADC10 module.

7. ADC10CTL0 and ADC10CTL1 are registers
a) for controlling SAR module
b) for controlling the sigma delta module
c) for controlling the comparator module
d) all of the mentioned

View Answer

Answer: a [Reason:] ADC10CTL0 and ADC10CTL1 are the registers that are used for controlling the SAR module in the MSP430.

8. While conversion is in progress, which of the flag is affected.
a) ADC10ON
b) ADC10MEM
c) ADC10BUSY
d) ADC10DF

View Answer

Answer: c [Reason:] While conversion is in progress, then ADC10BUSY flag is set.

9. ADC10SHTx bits allow_________cycles of the ADC10CLK.
a) 4
b) 8
c) 16
d) all of the mentioned

View Answer

Answer: d [Reason:] ADC10SHTx bits allow 4,8,16 and 64 cycles of the ADC10CLK.

10. The input to the ADC10 is selected from_______bits of the ADC10CTL1 register?
a) INCHx
b) ADC10SC
c) ADC10ON
d) ENC

View Answer

Answer: a [Reason:] The input to the ADC10 is selected from the INCHx bits of the ADC10CTL1 register.

Interview MCQ Set 4

1. Which of the following is the analog to digital converter that is present in the MSP430 based processors?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned

View Answer

Answer: d [Reason:] A comparator module, a successive approximation ADC module and a sigma delta ADC converters are found in the MSP based processors.

2. Higher resolution along with the slow speed is given by which ADC module?
a) comparator
b) successive approximation ADC
c) sigma delta ADC
d) all of the mentioned

View Answer

Answer: c [Reason:] Higher resolution along with the slow speed is given by the sigma delta ADC module.

3. The technical terms that helps us in differentiating between converters are:
a) resolution
b) accuracy
c) precision
d) all of the mentioned

View Answer

Answer: d [Reason:] While selecting the converter, necessary for our work we had to take care of the factors like resolution, accuracy and precision in it.

4. The number of repeated closeness to the true value is accounted by
a) resolution
b) accuracy
c) precision
d) all of the mentioned

View Answer

Answer: c [Reason:] The degree of closeness of the measured value to the actual true value is its accuracy, while on the other hand the measure of the repeated accuracy is termed as the precision.

5. Resolution is
a) change in measured value from the true value
b) the amount of change in the input value for the corresponding change of 1 unit in the output value
c) as the measure of the repeated accuracy
d) all of the mentioned

View Answer

Answer: b [Reason:] Resolution is defined as the amount of change in the input value for the corresponding change of 1 unit in the output value.

6. The process of reduction of a continuous input to a discrete output is
a) levelling
b) signalling
c) quantization
d) converting

View Answer

Answer: c [Reason:] The process of reduction of a continuous input to a discrete output is called as quantization.

7. Which of the following functions can be used for converting the nearest integer to its argument?
a) int
b) mint
c) uint
d) nint

View Answer

Answer: d [Reason:] nint is the function that is priorly used for converting the nearest integer to its argument.

8. Integral nonlinearity is termed as
a) process of reduction of a continuous input to a discrete output
b) change in measured value from the true value
c) maximum deviation between this corrected staircase and the actual transfer characteristic
d) the function used in quantization

View Answer

Answer: c [Reason:] Integral nonlinearity is termed as the maximum deviation between this corrected staircase and the actual transfer characteristic.

9. The SNR_______ with the increase of the number of bits.
a) remains constant
b) goes up
c) goes down
d) goes asymmetrically

View Answer

Answer: b [Reason:] The SNR goes up with te number of bits.

10. The intervals between the samples is obtained from
a) Fs
b) Ts
c) Us
d) Ks

View Answer

Answer: b [Reason:] The intervals between the samples is obtained by Ts that is equal to 1/fs.

Interview MCQ Set 5

1. Which of the following cannot be used to implement a timestamp
a) System clock
b) Logical counter
c) External time counter
d) None of the mentioned

View Answer

Answer: c [Reason:] An external time counter cannot be used to implement a timestamp. System clock and a logical counter can be used.

2. A logical counter is _________ after a new timestamp has been assigned
a) Incremented
b) Decremented
c) Doubled
d) Remains the same

View Answer

Answer: a [Reason:] A logical counter is incremented after a new timestamp has been assigned everytime.

3. W-timestamp(Q) denotes?
a) The largest timestamp of any transaction that can execute write(Q) successfully
b) The largest timestamp of any transaction that can execute read(Q) successfully
c) The smallest timestamp of any transaction that can execute write(Q) successfully
d) The smallest timestamp of any transaction that can execute read(Q) successfully

View Answer

Answer: a [Reason:] W-timestamp(Q) denotes The largest timestamp of any transaction that can execute write(Q) successfully.

4. R-timestamp(Q) denotes?
a) The largest timestamp of any transaction that can execute write(Q) successfully
b) The largest timestamp of any transaction that can execute read(Q) successfully
c) The smallest timestamp of any transaction that can execute write(Q) successfully
d) The smallest timestamp of any transaction that can execute read(Q) successfully

View Answer

Answer: b [Reason:] R-timestamp(Q) denoted the largest timestamp of any transaction that can execute read(Q) successfully.

5. A ________ ensures that any conflicting read and write operations are executed in timestamp order
a) Organizational protocol
b) Timestamp ordering protocol
c) Timestamp execution protocol
d) 802-11 protocol

View Answer

Answer: b [Reason:] A timestamp ordering protocol ensures that any conflicting read and write operations are executed in timestamp order.

6. The default timestamp ordering protocol generates schedules that are
a) Recoverable
b) Non-recoverable
c) Starving
d) None of the mentioned

View Answer

Answer: b [Reason:] The timestamp ordering protocol generates schedules that are non-recoverable. But it can be extended to make the schedules recoverable.

7. State true or false: The Thomas write rule has a greater potential concurrency than the timestamp ordering protocol
a) True
b) False

View Answer

Answer: a [Reason:] The Thomas write rule has a greater potential concurrency than the timestamp ordering protocol. This is because it is a modified version of the timestamp ordering protocol in which obsolete write operations can be ignored under certain circumstances.

8. Which of the following timestamp based protocols generates serializable schedules?
a) Thomas write rule
b) Timestamp ordering protocol
c) Validation protocol
d) None of the mentioned

View Answer

Answer: a [Reason:] Thomas write rule protocol generates serializable schedules that no other protocol can generate.

9. In timestamp ordering protocol, suppose that the transaction Ti issues read(Q) and TS(Ti)<W-timestamp(Q), then
a) Read operation is executed
b) Read operation is rejected
c) Write operation is executed
d) Write operation is rejected

View Answer

Answer: b [Reason:] Suppose that transaction Ti issues read(Q). If TS(Ti ) < W-timestamp(Q), then Ti needs to read a value of Q that was already overwritten. Hence, the read operation is rejected, and Ti is rolled back.

10. In timestamp ordering protocol, suppose that the transaction Ti issues write(Q) and TS(Ti)<W-timestamp(Q), then
a) Read operation is executed
b) Read operation is rejected
c) Write operation is executed
d) Write operation is rejected

View Answer

Answer: d [Reason:] In timestamp ordering protocol, suppose that the transaction Ti issues write(Q) and TS(Ti)<W-timestamp(Q), then the value of Q that Ti is producing was needed previously, and the system assumed that the value would never be produced. Hence the system rejects the write(Q) operation and the transaction Ti rolls back.

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