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Interview MCQ Set 1

1. Which of the following is correct?
a) I2C is a technique by which data is transmitted with the help of only eight pins
b) SDA is used to synchronize data transfer between two chips
c) TWI is an another name for I2C
d) All of the mentioned

View Answer

Answer: c [Reason:] I2C is a technique by which data is transmitted between two devices by the help of only 2 pins so it is also called as Two wire Serial Interface.

2. Which of the following is true about the I2C protocols?
a) the data line cannot change when the clock line is high
b) the data line can change when the clock line is high
c) the clock line cannot change when the data line line is high
d) the clock line can change when the data line is high

View Answer

Answer: a [Reason:] According to I2C protocols, the data line(SDA) changes only if the clock line(SCL) is at its active low level.

3. I2C is a connection oriented communication protocol.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] I2C is a connection oriented protocol i.e each transmission is initiated by a START condition and is terminated by a STOP condition.

4. The STOP condition is generated by a
a) high to low change in the SDA line when the SCL is low
b) high to low change in the SDA line when the SCL is high
c) low to high change in the SDA line when the SCL is low
d) low to high change in the SDA line when the SCL is high

View Answer

Answer: c [Reason:] The STOP condition is generated when their is a low to high change in the SDA line when the SCL is low.

5. For receiving the acknowledgement
a) SDA from transmitter should be high
b) SDA from transmitter should be low
c) SDA from receiver should be high
d) SDA from receiver should be low

View Answer

Answer: d [Reason:] The packet format in I2C consists of 9 bits, out of which first 8 are the data bits while the ninth bit is the acknowledgement bit. For obtaining the acknowledgement, the SDA line of the receiver should be pushed to low.

6. What steps are followed to complete the data transfer?
a) START condition, STOP condition
b) Address packet
c) One or more data packet
d) All of the mentioned

View Answer

Answer: d [Reason:] For having the complete data transfer, the steps that are actually being followed are START condition, address packet, one or more data packet, STOP condition.

7. I2C is ideal for short distances?
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] I2C is that module of the AVR, which is used for short distances.

8. Which of the following is a register used for programming AVR’s I2C module?
a) TWBR
b) TWCR
c) TWSR
d) All of the mentioned

View Answer

Answer: d [Reason:] TWBR( TWI Bit rate register), TWCR( TWI Control Register), TWSR(TWI Status Register), TWAR(TWI Address Register), TWDR( TWI Data Register) are used for programming a AVR’s I2C module.

9. Which bit is polled to know that whether the TWI is ready or not?
a) TWWC
b) TWINT
c) TWEA
d) All of the mentioned

View Answer

Answer: b [Reason:] TWINT is the bit that is polled to know that whether the TWI is ready or not.

10. Is status flag important in multi master systems?
a) yes
b) no
c) depends on the conditions
d) cant be said

View Answer

Answer:a [Reason:] Yes, status flag plays a very vital role in multi master systems.

Interview MCQ Set 2

1. Which of the following functions is not related to port P1?
a) P1SEL
b) P1DIR
c) P1IES
d) All of the mentioned

View Answer

Answer: d [Reason:] All these functions are related to the port P1.

2. A pull-up or pull-down resistor
a) removes the full output drive on the output pin
b) gives only a feeble current through the pull-up to resistor
c) both of the mentioned
d) none of the mentioned

View Answer

Answer: c [Reason:] A pull-up or pull-down resistor is used to remove the full output drive on the output pin. It also gives a feeble current through the pull-up to resistor.

3. P1.3 is the
a) input CCI1A to Timer_A
b) is connected to the voltage reference VREF of SD16_A
c) is output TA0 from Timer_A
d) are digital inputs with pull-up resistors

View Answer

Answer: b [Reason:] P1.3 is connected to the voltage reference VREF of SD16_A.

4. What actually is SD16_A?
a) it is an interrupt
b) it is a timer
c) it is an analog to Digital Converter
d) it is a serial communication module

View Answer

Answer: c [Reason:] SD16_A is an analog to digital module.

5. P1IE and P1IES are registers that are used to
a) control the Port1 digital i/o ports
b) control the Port1 interrupts
c) control the Port1 serial communication interfaces
d) all of the mentioned

View Answer

Answer: b [Reason:] P1IE and P are used to control the Port1 interrupts.

6. Unused pins must never be left unconnected in their default state as inputs.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] Unused pins must never be left unconnected in their default state as inputs. This follows a general rule that inputs to CMOS must never be left unconnected or “floating”.

7. Which of the following is an effect of a Schmidt trigger?
a) it turns slowly varying inputs, which might cause problems while they pass slowly through the undefined range of input voltages, into abrupt, clean logical transitions
b) It eliminates the effect of noise on the input, provided that it is not large enough to span the gap between the upward and downward thresholds
c) none of the mentioned
d) all of the mentioned

View Answer

Answer: d [Reason:] Scmidt trigger has two of the above mentioned effects in it.

8. To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the input down through VIT−, we must choose
a) minimum hysteresis
b) maximum hysteresis
c) all of the mentioned
d) none of the mentioned

View Answer

Answer: a [Reason:] To ensure that a negative fluctuation does not trigger an unwanted downward transition by pulling the input down through VIT−, we must choose a minimum hysteresis of 0.3V.

9. The SPDT switch can be used as a
a) detecting circuit
b) debouncing circuit
c) devaluing circuit
d) dejunerrating circuit

View Answer

Answer: b [Reason:] The SPDT(single pole, double pole) switch can be used as a debouncing circuit of a switch.

10. Debouncing can be carried out at a hardware as well as the software end?
a) yes
b) no
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] Debouncing can be carried out at both the fronts both at the software as well as the hardware front, to carry out the process appropriately.

Interview MCQ Set 3

1. The watchdog counts up and resets the MSP430 when it reaches the limit?
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] The watchdog timer is used for the protection of the device. It keeps a track at the counter so that the code doesnot reach an infinite unending loop. So it actually resets the counter before this particular condition.

2. Which of the following is correct about WDTCTL?
a) it is a 16 bit register
b) it is guided against accidental writes that require a password
c) a reset will occur if a value with an incorrect password is written to WDTCTL
d) all of the mentioned

View Answer

Answer: d [Reason:] WDTCTL is a 16 bit register that is used for protecting the microcontroller. It actually resets the value when an incorrect password is written to WDTCTL.

3. WDTNMI is found in the
a) higher byte of WDTCTL
b) lower byte of WDTCTL
c) its first four bits
d) its last four bits

View Answer

Answer: b [Reason:] WDTNMI is the fifth bit of the WDTCTL register.

4. Which of the following bits reads 0 under normal conditions but goes 1 when it wants to initiate some action?
a) WDTNMI
b) WDTHOLD
c) WDTTMSEL
d) WDTCNTCL

View Answer

Answer: d [Reason:] WDTCNTCL is the bit that reads 0 under normal conditions but goes 1 when it wants to initiate some action like resetting the counter.

5. WDTISx bits control the
a) period of the clock
b) act as “Nonmaskable Interrupts”
c) stop the watchdog timer
d) start the watchdog timer

View Answer

Answer: a [Reason:] WDTISx bits of the WDTCTL register are responsible for controlling the period of the clock.

6. The process of setting the WDTCNTCL bit in WDTCTL is through
a) petting
b) feeding
c) kicking
d) all of the mentioned

View Answer

Answer: d [Reason:] the process of setting the WDTCNTCL bit in the WDTCTL register is by the processes like petting, feeding and kicking.

7. What is the function of this instruction “WDTCTL = WDTPW | WDTCONFIG”, where **#define WDTCONFIG (WDTCNTCL|WDTSSEL)**
a) it sets the watchdog timer
b) it configures and clears the watchdog timer
c) it stops the watchdog timer
d) it configures and sets the watchdog timer

View Answer

Answer: b [Reason:] WDTCTL = WDTPW | WDTCONFIG instruction is used to clear and configure the watchdog timer of a micro controller.

8. Is this instruction correct?
WDTCTL_bit.WDTCNTCL = 1;
a) yes
b) no
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] No WDTCTL_bit.WDTCNTCL = 1; is an incorrect way of setting the bits of the WDTCTL register because it violates the password protection.

9. Setting the WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as
a) interrupt
b) communication device
c) converter
d) interval timer

View Answer

Answer: d [Reason:] The WDTTMSEL bit of the WDTCTL register makes the watchdog timer act as the interval timer.

10. WDTIFG flag gets cleared if
a) if is interrupt had occurred
b) if the interrupt is serviced
c) if there can be no interrupt
d) all of the mentioned

View Answer

Answer: b [Reason:] WDTIFG flag gets cleared if the interrupt is serviced, so that again the interrupt can occur.

Interview MCQ Set 4

1. The basic idea behind the sigma delta converter is that
a) to carry out the conversion
b) to carry out communication
c) to reduce the circuit to its simplest way possible and then carry out the conversion
d) all of the mentioned

View Answer

Answer: c [Reason:] The main idea behind the sigma delta converter is that to reduce the circuit to its simplest way possible and then carry out the conversion.

2. Sigma delta converter is a
a) 1 bit converter
b) 2 bit converter
c) 3 bit converter
d) 4 bit converter

View Answer

Answer: a [Reason:] Sigma delta converter is a 1 bit converter.

3. Sigma delta converter is having good resolution.
a) yes
b) no
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] Sigma delta converter is having poor resolution quality.

3. Oversampling ratio is defined as the
a) final frequency
b) oversampling frequency
c) oversampling frequency/final frequency
d) final frequency/oversampling frequency

View Answer

Answer: c [Reason:] Oversampling ratio is defined as the ration of the oversampling frequency fm to the final frequency fs.

4. Here the word sigma represents
a) subtraction
b) differentiation
c) integration
d) none of the mentioned

View Answer

Answer: c [Reason:] In a sigma delta converter, sigma word represents that the output obtained from the delta function is getting integrated.

5. SD16_A features are controlled by
a) memory mapped registers
b) register mapped registers
c) data mapped registers
d) none of the mentioned

View Answer

Answer: a [Reason:] SD16_A features are controlled by the memory mapped registers.

6. The second part of the ADC handles purely digital signals.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] The second part of the ADC handles purely digital signals.

7. The second part of the ADC’s output is in the form of
a) the fast stream of single bits
b) the fast stream of multiple bits
c) the slow stream of single bits
d) the slow stream of multiple bits

View Answer

Answer: d [Reason:] The second part of the ADC take in fast stream of singe bit and give out slow stream of multiple bit values.

8. The filtered digital signal is then decimated to
a) reduce the rate of samples from fm to fs
b) reduce the rate of samples from fs to fm
c) increase the rate of samples from fm to fs
d) increase th rate of samples from fs to fm

View Answer

Answer: a [Reason:] The filtered digital output is then decimated in order to reduce the rate of samples from fm to fs.

9. Decimated means
a) multipled by 10
b) multiplied by 100
c) divided by 10
d) divided by 100

View Answer

Answer: c [Reason:] Decimated means to divide the result by 10.

10. The SD16 has a second-order modulator with a
a) sinc filter
b) sinc2 filter
c) sinc3 fiter
d) rect filter

View Answer

Answer: c [Reason:] The SD16 has a second-order modulator with a sinc3 filter.

Interview MCQ Set 5

1. Their are how many MSP430’s low power modes available in the chip?
a) two
b) three
c) four
d) five

View Answer

Answer: d [Reason:] There are five low power modes available in the MSP430, out of which two are rarely employed in the current devices.

2. Which of the following are the low power modes?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned

View Answer

Answer: d [Reason:] LPM0, LPM3, LPM4 all are the low power modes that are available in the MSP430.

3. Which of the following modes is also known as the RAM retention mode?
a) LPM0
b) LPM3
c) LPM4
d) All of the mentioned

View Answer

Answer: c [Reason:] LPM4 is known as the RAM retention mode. Here, the CPU and all clocks are disabled, I ≈ 0.1A. The device can be wakened only by an external signal.

4. Waking a device simply means that switching that device’s operation from a low power mode to an active mode.
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: a [Reason:] When a device is operating in a low power mode, it can also be assumed that the device is sleeping, so waking a device simply means to turn that device’s operation from a low power mode to an active mode.

5. When an interrupt is accepted, the contents of the status register are
a) set
b) reset
c) remains the same
d) cant be said

View Answer

Answer:b [Reason:] When any interrupt is accepted, the contents of the status register are cleared, it actually puts the processor in the active mode.

6. MCLK must first be started
a) for synchronization
b) for input
c) for CPU to handle the interrupts
d) none of the mentioned

View Answer

Answer: c [Reason:] MCLK must first be started for CPU to handle the interrupts.

7. _ _low_ power_mode_0() states the processor to
a) enable the interrupt
b) disable the interrupt
c) nothing
d) to go in an active mode

View Answer

Answer: a [Reason:] _ _low_ power_mode_0() puts the processor in the LPM0 mode.

8. More power can be saved by using low_power mode 0 than low_power mode 3
a) true
b) false
c) cant be said
d) depends on the conditions

View Answer

Answer: b [Reason:] More power is saved in low_ power mode 3.

9. _BIC_SR_IRQ() is used to
a) set the particular bits of the SR
b) reset the particular bits of the SR
c) any of the above mentioned depending on the conditions
d) none of the mentioned

View Answer

Answer: b [Reason:] _BIC_SR_IRQ() is used to clear the bits of the SR.

10. The only clock that runs in the LPM3 is the
a) MCLK
b) ACLK
c) CLK
d) None of the mentioned

View Answer

Answer: b [Reason:] The only clock that runs in the LPM3 is the ACLK.

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