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Interview MCQ Set 1

1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out

View Answer

Answer: c [Reason:] The stack follows last-in-first-out sequence.

2. If the processor is executing a main program that calls a subroutine, then after executing the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned

View Answer

Answer: b [Reason:] Since subroutine is called, to start the execution of subroutine, the control is transferred to the subroutine address.

3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned

View Answer

Answer: d [Reason:] Stack is used for temporary storage of contents of registers and memory locations, status of registers.

4. The Stack is accessed using
a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned

View Answer

Answer: c [Reason:] The stack is accessed using a pointer that is implemented using SP and SS registers.

5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2

View Answer

Answer: d [Reason:] The data is stored from top address of the stack and is decremented by 2.

6. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2

View Answer

Answer: b [Reason:] The data in the stack, may again be transferred back from stack to register. At that time, the stack pointer is incremented by 2.

7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into

View Answer

Answer: c [Reason:] The data is pushed into the stack while loading the stack.

8. The reverse process of transferring the data back from the stack to the CPU register is known as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack

View Answer

Answer: d [Reason:] The data retrieved from stack is called popping off.

9. The books arranged one on the other on a table is an example of
a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out

View Answer

Answer: d [Reason:] If the books are arranged one on the other, then the book that is placed last will be the first out.

10. The PID temperature controller using 8086 has
a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack

View Answer

Answer: d [Reason:] Since PID temperature controller has steps that are need to be sequentially executed such as sampling the output, conversion of signal with ADC, finding errors, deriving control signals and applying control signal to control flow of energy.

Interview MCQ Set 2

1. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment

View Answer

Answer: c [Reason:] The stack pointer register contains the offset of the address of the stack segment.

2. The stack segment register contains
a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment

View Answer

Answer: b [Reason:] The stack segment register contains base address of the stack segment in the memory. The stack pointer register (sP) and stack segment register (SS) together address the stack-top.

3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS

View Answer

Answer: a [Reason:] Each PUSH operation decrements the SP ( Stack Pointer) register.

4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS

View Answer

Answer: b [Reason:] Each POP operation increments the SP ( Stack Pointer) register.

5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last

View Answer

Answer: c [Reason:] The data can be retrieved by POP operation and as in stack, the data that is pushed at the end must be popped off first.

6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK
the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments

View Answer

Answer: d [Reason:] The directive ASSUME facilitates to name the segments with desired name that is not a mnemonic or keyword.

7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised

View Answer

Answer: a [Reason:] Though the Stack segment is initialised, the SS and SP pointers must be initialised.

8. The number of PUSH instructions and POP instructions in a subroutine must be
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind

View Answer

Answer: c [Reason:] The number of PUSH instructions must be equal to the number of POP instructions.

9. 8086 does not support
a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication

View Answer

Answer: d [Reason:] The 8086 microprocessor does not support direct BCD packed operations.

10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE

View Answer

Answer: b [Reason:] In 8086 microprocessor, the memory segments each have a memory of 64K bytes.

Interview MCQ Set 3

1. The stage in which the CPU fetches the instructions from the instruction cache in superscalar organisation is
a) Prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) Final stage

View Answer

Answer: a [Reason:] In the prefetch stage of pipeline, the CPU fetches the instructions from the instruction cache, which stores the instructions to be executed. In this stage, CPU also aligns the codes appropriately.

2. The CPU decodes the instructions and generates control words in
a) Prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) Final stage

View Answer

Answer: b [Reason:] In D1 stage, the CPU decodes the instructions and generates control words. For simple RISC instructions, only single control word is enough for starting the execution.

3. The fifth stage of pipeline is also known as
a) read back stage
b) read forward stage
c) write back stage
d) none of the mentioned

View Answer

Answer: c [Reason:] The fifth stage or final stage of pipeline is also known as “Write back (WB) stage”.

4. In the execution stage the function performed is
a) CPU accesses data cache
b) executes arithmetic/logic computations
c) executes floating point operations in execution unit
d) all of the mentioned

View Answer

Answer: d [Reason:] In the execution stage, known as E-stage, the CPU accesses data cache, executes arithmetic/logic computations, and floating point operations in execution unit.

5. The stage in which the CPU generates address for data memory references in this stage is
a) prefetch stage
b) D1 (first decode) stage
c) D2 (second decode) stage
d) execution stage

View Answer

Answer: c [Reason:] In the D2 (second decode) stage, CPU generates address for data memory references in this stage. This stage is required where the control word from D1 stage is again decoded for final execution.

6. The feature of separated caches is
a) supports the superscalar organisation
b) high bandwidth
c) low hit ratio
d) all of the mentioned

View Answer

Answer: d [Reason:] The seperated caches have low hit ratio compared to a unified cache, but have the advantage of supporting the superscalar organisation and high bandwidth.

7. In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from
a) floating point unit
b) instruction cache
c) floating point register file or data cache
d) floating point register file or instruction cache

View Answer

Answer: c [Reason:] In the operand fetch stage, the FPU (Floating Point Unit) fetches the operands from either floating point register file or data cache.

8. The FPU (Floating Point Unit) writes the results to the floating point register file in
a) X1 execution state
b) X2 execution state
c) write back stage
d) none of the mentioned

View Answer

Answer: c [Reason:] In the two execution stages of X1 and X2, the floating point unit reads the data from the data cache and executes the floating point computation. In the “write back stage” of pipeline, the FPU (Floating Point Unit) writes the results to the floating point register file.

9. The floating point multiplier segment performs floating point multiplication in
a) single precision
b) double precision
c) extended precision
d) all of the mentioned

View Answer

Answer: d [Reason:] The floating point multiplier segment performs floating point multiplication in single precision, double precision and extended precision.

10. The instruction or segment that executes the floating point square root instructions is
a) floating point square root segment
b) floating point division and square root segment
c) floating point divider segment
d) none of the mentioned

View Answer

Answer: c [Reason:] The floating point divider segment executes the floating point division and square root instructions.

11. The floating point rounder segment performs rounding off operation at
a) after write back stage
b) before write back stage
c) before arithmetic operations
d) none of the mentioned

View Answer

Answer: b [Reason:] The results of floating point addition or division process may be required to be rounded off, before write back stage to the floating point registers.

12. Which of the following is a floating point exception that is generated in case of integer arithmetic?
a) divide by zero
b) overflow
c) denormal operand
d) all of the mentioned

View Answer

Answer: d [Reason:] In the case of integer arithmetic, the possible floating point exceptions in Pentium are: 1. divide by zero 2. overflow 3. denormal operand 4. underflow 5. invalid operation.

13. The mechanism that determines whether a floating point operation will be executed without creating any exception is
a) Multiple Instruction Issue
b) Multiple Exception Issue
c) Safe Instruction Recognition
d) Safe Exception Recognition

View Answer

Answer: c [Reason:] A mechanism known as Safe Exception Recognition (SER) had been employed in Pentium which determines whether a floating point operation will be executed without creating any exception.

Interview MCQ Set 4

1. The processors used in the multimicroprocessor are
a) coprocessors
b) independent processors
c) coprocessors or independent processors
d) none of the mentioned

View Answer

Answer: c [Reason:] The processors used in the multimicroprocessor are either coprocessors or independent processors.

2. The processor that executes the instructions fetched for it by the host processor is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor

View Answer

Answer: b [Reason:] The coprocessor executes the instructions fetched for it by the host processor.

3. The processor that asks for bus access or may itself fetch the instructions and execute them is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor

View Answer

Answer: c [Reason:] The independent processor may ask for bus access, may fetch the instructions itself, and execute them independently.

4. In tightly coupled systems, the microprocessors share
a) common clock
b) bus control logic
c) common clock and bus control logic
d) none of the mentioned

View Answer

Answer: c [Reason:] The microprocessors share a common clock and bus control logic, in a tightly coupled system.

5. Communication between processors using a common system bus and common memory takes place in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned

View Answer

Answer: b [Reason:] In tightly coupled systems, the two processors may communicate using a common system bus or common memory.

6. The bus arbitration is handled by an external circuit in
a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
d) none of the mentioned

View Answer

Answer: a [Reason:] In loosely coupled multiprocessor system, each CPU may have its own bus control logic. The bus arbitration is handled by an external circuit, common to all the processors.

7. The loosely coupled system has an advantage of
a) more number of CPUs can be added
b) system structure is modular
c) more fault-tolerant and suitable for parallel applications
d) all of the mentioned

View Answer

Answer: d [Reason:] The loosely coupled system is advantageous than tightly coupled system as it has advantages of more number of CPUs can be added to improve the system performance. A fault in a single module does not lead to a complete system breakdown.

8. In a tightly coupled system, when a processor is using the bus then the local bus of other processors is in
a) hold state
b) high impedance state
c) halt state
d) low impedance state

View Answer

Answer: b [Reason:] When a processor is using the bus then the other processors maintain their local buses in high impedance state.

9. The disadvantage of loosely coupled system is
a) complex due to additional hardware
b) less portable
c) more expensive
d) all of the mentioned

View Answer

Answer: d [Reason:] The loosely coupled systems are more complicated due to the required additional communication hardware. They are less portable and more expensive due to additional hardware.

10. To indicate the completion of task allocated in a closely (tightly) coupled system, the microprocessor uses
a) status bit in memory
b) interrupts the host
c) status bit in memory or interrupts the host
d) clock pulse

View Answer

Answer: c [Reason:] The microprocessor in a closely coupled system either uses a status bit in memory or interrupts the host to inform it about the completion of task allotted to it.

Interview MCQ Set 5

1. If ‘n’ denotes number of clock cycles and ‘T’ denotes period of the clock at which the microprocessor is running, then duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T

View Answer

Answer: c [Reason:] The duration of execution of the loop is the product of number of clock cycles and the period of the clock cycle at which microprocessor is running.

2. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration

View Answer

Answer: b [Reason:] As the microprocessor executes each instruction corresponding loop counter value decreases and the microprocessor executes the instructions till loop counter becomes zero.

3. In case of subroutines, the actual number of instructions executed by the processor depends on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none

View Answer

Answer: c [Reason:] In case of subroutines or interrupt service routines, the number of instructions executed by the processor depends on the length of procedure (or subroutine) or length of interrupt service routine along with the main calling program.

4. The step included in generating delays is
a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned

View Answer

Answer: d [Reason:] The delays can be generated step wise.

5. The Count, N can be defined as
a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency

View Answer

Answer: a [Reason:] The count N can be defined as the required time delay by the duration for execution of the loop once. Count, N = required delay (Td)/duration for execution of the loop once (n*T).

6. In the instruction set,

      MOV CX, BA03H
WAIT: DEC CX
      NOP
      JNZ WAIT
      RET

if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles

View Answer

Answer: d [Reason:] The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.

7. In the above instruction set, if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles

View Answer

Answer: c [Reason:] The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.

8. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay

View Answer

Answer: d [Reason:] The maximum count value of 16-bit count register is FFFFH. This may put limitation on the maximum delay that can be generated using the instructions.

9. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used

View Answer

Answer: a [Reason:] One or more count registers can be used to serve large delays.