Select Page
Generic selectors
Exact matches only
Search in title
Search in content
Search in posts
Search in pages
Filter by Categories
nmims post
Objective Type Set
Online MCQ Assignment
Question Solution
Solved Question
Uncategorized

## Interview MCQ Set 1

1. The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none

Answer: b [Reason:] The semiconductor memories are organised as two dimension of array which consists of rows and columns.

2. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
c) data bus
d) either address bus or data bus

Answer: c [Reason:] The bits in a selected location are accessible using data bus.

3. To address a memory location out of N memory locations, the number of address lines required is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)

Answer: a [Reason:] For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of memory, 12 address lines are required since log(4KB) =log(4*1024)=log(212)=12.

4. If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
a) 512
b) 1024
c) 2048
d) none

Answer: b [Reason:] Since for n address lines, the number of memory locations able to address is 2^n.

5. In static memory, the upper 8-bit bank of available 16-bit memory chip is called
c) static upper memory

Answer: d [Reason:] In static memory, the upper 8-bit bank is called odd address memory bank.

6. In static memory, the lower 8-bit bank of available 16-bit memory chip is called
c) static lower memory bank

Answer: b [Reason:] In static memory, the lower 8-bit bank is called even address memory bank.

7. In most of the cases, the method used for decoding that may be used to minimise the required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none

Answer: c [Reason:] In general, linear decoding is used to minimise the required hardware.

8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel

Answer: a [Reason:] The two 4K*8 chips of RAM and ROM are arranged in parallel.

9. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM

Answer: c [Reason:] If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.

10. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM

Answer: c [Reason:] If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected.

## Interview MCQ Set 2

1. The serial communication is
a) cheaper communication
b) requires less number of conductors
c) slow process of communication
d) all of the mentioned

Answer: d [Reason:] The serial communication requires less number of conductors and thus it is cheaper. It is slow as the bits are transmitted one by one along with start, stop and parity bits.

2. The serial communication is used for
a) short distance communication
b) long distance communication
c) short and long distance communication
d) communication for a certain range of distance

Answer: b [Reason:] Serial communication is more popular for communication over longer distances as it requires less number of conductors.

3. The mcs 51 architecture supports
a) serial transmission and reception
b) simultaneous transmission and reception
c) transmission and reception of data using serial communication interface
d) all of the mentioned

Answer: d [Reason:] The mcs 51 architecture supports simultaneous transmission and reception of binary data byte by byte i.e. full duplex mode of communication. It supports serial transmission and reception of data using standard serial communication interface and baud rates.

4. The number of bits transmitted or received per second is defined as
a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate

Answer: d [Reason:] Here, baud rate can be defined as the number of bits transmitted or received per second.

5. The task of converting the byte into serial form and transmitting it bit by bit along with start, stop and parity bits is carried out by
a) reception unit
b) serial communication unit
c) transmission unit
d) all of the mentioned

Answer: c [Reason:] the serial communication unit consists of transmission unit and reception unit. The task of converting the byte into serial form and transmitting it bit by bit along with start, stop and parity bits is carried out by transmission unit.

6. The transmission unit does not require assistance from processor if once a byte for transmission is written to
a) SCON register
b) SBUF register
d) Any of the mentioned

Answer: b [Reason:] once a byte for transmission is written to the serial buffer(SBUF) register, the transmission unit does not require assistance from processor.

7. The common unit shared by the receiver unit and transmission unit of serial communication unit is
a) SCON(Serial Port Control) Register
b) SBUF(Serial Buffer) register
c) 8-bit serial data interface
d) All of the mentioned

Answer: d [Reason:] The transmission unit and receiver unit both are controlled by using a common SCON(Serial Port Control) Register. Also both units share a common serial buffer(SBUF) register which is a common 8-bit serial data interface.

8. During serial reception, the buffer that receives serial bits and converts to a byte is
d) none

Answer: b [Reason:] During serial reception, the receive buffer 1 receives serial bits and converts to a byte, it then transfers the received parallel byte in receive buffer 2.

9. If SM0=1, SM1=0, then the transceiver selected is
a) 8-bit synchronous
b) 9-bit synchronous
c) 8-bit asynchronous
d) 9-bit asynchronous

Answer: d [Reason:] If SM0=1, SM1=0, then the 9-bit asynchronous transceiver is selected.

10. If the microcontroller is expected to communicate in multiprocessor system, then the required condition is
a) SM0 is set
b) SM1 is set
c) SM2 is set
d) REN is set

Answer: c [Reason:] The bit, SM2 is set if the microcontroller is expected to communicate in multiprocessor system.

11. In mode 2, the baud rate depends only on
a) SMOD bit
b) SCON bit
c) Oscillator clock frequency
d) SMOD bit and oscillator clock frequency

Answer: d [Reason:] In mode 2, the baud rate depends only on SMOD bit and oscillator clock frequency.

12. The mode that offers the most secured parity enabled data communication at lower baud rates is
a) mode 2
b) mode 1
c) mode 0
d) all of the mentioned

Answer: a [Reason:] The mode 3 offers the most secured parity enabled data communication at lower baud rates of mode 1.

## Interview MCQ Set 3

1. The 80286 is available in package as
a) 68-pin PLCC (plastic leaded chip carrier)
b) 68-pin LCC (lead less chip carrier)
c) 68-pin PGA (pin grid array)
d) all of the mentioned

Answer: d [Reason:] The 80286 is available in 68-pin PLCC (plastic leaded chip carrier), 68-pin LCC (lead less chip carrier) and 68-pin PGA (pin grid array) packages.

2. The clock frequency applied at the CLK pin is internally divided by
a) 2
b) 4
c) 8
d) 1

Answer: a [Reason:] The clock frequency is divided by two internally, and is used for deriving fundamental timings for basic operations of the circuit.

3. The 8 address lines, A23-A16 of 80286 are zero during
a) memory transfer
c) memory to processor transfer
d) I/O transfer

Answer: d [Reason:] The address lines, A23-A16 are zero during I/O transfers.

4. The signals S1 (active low), S2 (active low) are
a) output signals
b) indicate initiation of bus cycle
c) define type of bus cycle with M/IO (active low)
d) all of the mentioned

Answer: d [Reason:] The signals S1 (active low), S2 (active low) are active low status output signals, which indicate initiation of a bus cycle, and with M/IO (active low) and COD/INTA (active low), they define the type of the bus cycle.

5. If M/IO (active low) signal is ‘0’ then it indicates
a) I/O cycle
b) Memory cycle
c) I/O cycle or INTA cycle
d) I/O cycle or HALT cycle

Answer: c [Reason:] If M/IO (active low) signal is ‘0’ then it indicates that an I/O cycle or INTA cycle is in process, and if it is ‘1’, it indicates that a memory or a HALT cycle is in progress.

6. The LOCK (active low) is activated automatically by hardware using
a) XCHG signal
b) Interrupt acknowledge
c) Descriptor table access
d) All of the mentioned

Answer: d [Reason:] The lock pin is used to prevent the other masters from gaining the control of the bus, for the current and the following bus cycles. This pin is activated by a “LOCK” instruction prefix, or automatically by hardware during XCHG, interrupt acknowledge or descriptor table access.

7. The pin that is used to insert wait states in a bus cycle is
a) WAIT
b) BHE (active low)
d) WAIT(active low)

Answer: c [Reason:] The active low READY pin is used to insert wait states in a bus cycle, for interfacing low speed peripherals. This signal is neglected during HLDA cycle.

8. The minimum number of clock cycles required in an input pulse width of RESET pin is
a) 4
b) 2
c) 8
d) 16

Answer: d [Reason:] The active high RESET input clears the internal logic of 80286, and re-initializes it. The reset input pulse width should be at least 16 clock cycles.

9. To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
a) CAP and ground
b) Output pin and ground
c) CAP and Vcc
d) NMI and ground

Answer: a [Reason:] A 0.047microfarads, 12V capacitor is connected between the CAP pin and ground, to filter the output of the internal substrate bias generator.

10. The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions is
a) BUSY (active low)
b) PEACK (active low)
c) PEREQ
d) ERROR (active low)

Answer: d [Reason:] An active ERROR (active low) signal causes the 80286 to perform the processor extension interrupt, while executing the WAIT and ESC instructions.

## Interview MCQ Set 4

1. The interconnection topologies are implemented using _________ as a node.
a) control unit
b) microprocessor
c) processing unit
d) microprocessor or processing unit

Answer: d [Reason:] The microprocessors or processing unit are used as a node in interconnection topologies. They may also work as stand-alone processors or subprocessing units, under the control of other microprocessors or processing units.

2. The feature of multimicroprocessor architecture is
b) single bus provider for many processors
c) design is for a specific task
d) all of the mentioned

Answer: d [Reason:] The main feature of multimicroprocessor is that it is task dependent. If it is designed for a specific task, then it may not be useful for other tasks.

3. The main objective in building the multimicroprocessor is
a) greater throughput
b) enhanced fault tolerance
c) greater throughput and enhanced fault tolerance
d) none of the mentioned

Answer: c [Reason:] Greater throughput and enhanced fault tolerance are the main objectives of multimicroprocessor system. These systems incorporate multiplicity of hardware and software, for the purpose.

4. An interface between the user or an application program, and the system resources is
a) microprocessor
b) microcontroller
c) multimicroprocessor
d) operating system

Answer: d [Reason:] The operating system acts as interface, and is an important program that resides in the computer memory.

5. An operating system provides
a) hardware and software resource management
b) input/output management
c) memory management
d) all of the mentioned

Answer: d [Reason:] An operating system provides a means of hardware and software resource management including input/output and memory management.

6. Distributed systems are designed to run
a) serial process
b) parallel process
c) serial and parallel process
d) none of the mentioned

Answer: d [Reason:] Distributed systems are designed to run parallel process. It is essential that a proper environment exists for concurrent processes to communicate and cooperate, in order to complete the alloted task.

7. A distributed operating system must provide a mechanism for
a) intraprocessor communication
b) intraprocess and intraprocessor communication
c) interprocess and interprocessor communication
d) interprocessor communication

Answer: c [Reason:] A distributed operating system must provide a mechanism for interprocess and interprocessor communication.

8. A multiprocessor operating system should perform
b) optimise the system performance
c) handling structural or architectural changes
d) all of the mentioned

Answer: d [Reason:] A multiprocessor operating system should have a mechanism to split a task, optimise system performance, and should handle structural changes.

9. An operating system must possess
a) process-processor allocation strategies
b) mechanism to collect results of subtasks
c) software to improve overall performance
d) all of the mentioned

Answer: d [Reason:] An operating system must have process-processor allocation strategies, mechanism to collect results of subtasks and software to improve overall performance.

10. A multiprocessor operating system must take care of
a) authorised data access and data protection
b) unauthorised data access and data protection
c) authorised data access
d) data protection

Answer: b [Reason:] A multiprocessor operating system must take care of unauthorised data access and data protection.

## Interview MCQ Set 5

1. Which of the following operation is not carried out by 80286?
b) halt
c) processor reset
d) none of the mentioned

Answer: d [Reason:] The 80286 carries out six operations. They are: 1. processor reset and initialization 2. task switch operation 3. pointer testing instructions 4. protected mode initialization 5. how to enter protected mode? 6. halt.

2. After completion of first cycle, the first task is again scheduled for the next cycle. This process is known as
a) repetition
c) processor initiation
d) none of the mentioned

Answer: b [Reason:] After completion of first cycle, the first task is again scheduled for the next cycle, and the process continues. The previous task that was incomplete, may be completed during its coming turns of the allotted CPU time slice. This switch-over operation from one task to another is called task switch operation.

3. The operation that is provided by the internal architecture, to save the execution state of a task is
a) processor reset
b) processor initialization
d) halt

Answer: c [Reason:] The 80286 internal architecture provides a task switch operation, to save the execution state of a task, and to load a new task to be executed.

4. The instruction that can be used to carry out task switch operation is
a) software interrupt instruction
b) exception
c) external interrupt
d) all of the mentioned

Answer: d [Reason:] A software interrupt instruction, exception or external interrupt, can also be used to carry out task switch operation.

5. The IRET instruction gets back the execution state of the previous task, if
a) NT (nested task flag) = 1
b) NT (nested task flag) = 0
c) IF (interrupt flag) = 1
d) IF (interrupt flag) = 0

Answer: a [Reason:] If NT = 1, the IRET instruction gets back the execution state of the previous task. Otherwise, the IRET instruction lets the current task continue, after popping the required values from stack.

6. The NT flag is set by the task switch operation, that is initiated by
a) CALL
b) INT
c) CALL & INT
d) None of the mentioned

Answer: c [Reason:] The NT flag is set by CALL or INT initiated task switch operations.

7. The 80286 executes LMSW instruction to enter into
b) protected mode
c) real addressing and protected modes
d) none of the mentioned

Answer: b [Reason:] To enter into protected mode, 80286 executes LMSW instruction, that sets PE flag.

8. The instruction that sets the zero flag, if the segment referred to, by the selector can be read is
a) VERW
b) VERR
c) LSL
d) LAR

Answer: b [Reason:] The VERR (VERify to Read) instruction sets the zero flag, if the segment referred to, by the selector, can be read.

9. The instruction that sets the zero flag, if the segment referred to by the selector, can be written as
a) VERW
b) APRL
c) LSL
d) LAR

Answer: a [Reason:] The VERW (VERify to Write) instruction sets the zero flag, if the segment referred to, by the selector can be written.

10. The instruction that reads the descriptor access rights byte into the register is
a) VERW
b) APRL
c) LSL
d) LAR

Answer: d [Reason:] The LAR (Load Access Rights) instruction reads the descriptor access rights byte into the register, if privilege rules allow.

11. The instruction that reads the segment limit into the register, if privilege rules and descriptor type allow is
a) VERW
b) APRL
c) LSL
d) LAR