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Interview MCQ Set 1

1. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a prefix of
a) X
b) E
c) 32
d) XX

View Answer

Answer: b [Reason:] A 32 bit register, known as extended register, is represented by the register name with a prefix of E.

2. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
a) LSP
b) FSP
c) SP
d) None of the mentioned

View Answer

Answer: c [Reason:] Though the extended size of 32 bits are named as EBP, ESP, ESI and EDI, the names BP, SP, SI and DI represent the lower 16-bits.

3. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) All of the mentioned

View Answer

Answer: d [Reason:] The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS, out of which DS, ES, FS and GS are the four data segment registers.

4. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned

View Answer

Answer: d [Reason:] The 32-bit addressing modes may use all the register widths, i.e. 8, 16 or 32 bits.

5. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) None of the mentioned

View Answer

Answer: c [Reason:] The VM and RF flags are added to the 80286 flag register, to derive the flag register of 80386.

6. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned

View Answer

Answer: b [Reason:] If VM flag is set, the 80386 enters the virtual 8086 mode within the protected mode. This is to be set only when the 80386 is in protected mode.

7. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) Task switch operation
c) IRET instruction or task switch operation
d) None of the mentioned

View Answer

Answer: c [Reason:] The VM flag can be set using the IRET instruction or any task switch operation, only in the protected mode.

8. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set

View Answer

Answer: d [Reason:] If RF (resume flag) is set, any debug fault is ignored during the instruction cycle.

9. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF

View Answer

Answer: c [Reason:] The RF is automatically reset after the execution of every instruction, except for the IRET and POPF instructions. Also, it is not cleared automatically after the successful execution of JMP, CALL and INT instructions causing a task switch.

10. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned

View Answer

Answer: d [Reason:] The segment descriptor register is used to store the descriptor information like attributes, limit and base addresses of segments.

Interview MCQ Set 2

1. Which of the following is an 8-bit register?
a) PSW(Program Status Word)
b) TCON(Timer Control Register)
c) Accumulator
d) All of the mentioned

View Answer

Answer: d [Reason:] The registers, PSW, TCON and Accumulator are 8-bit registers.

2. Which of the following register can be addressed as byte?
a) P1
b) SCON
c) TMOD
d) TCON

View Answer

Answer: c [Reason:] The registers, TMOD, SP, TH0, TH1, TL0, TL1 are to be addressed as bytes.

3. Which of the following is bit-addressable register?
a) SBUF
b) PCON
c) TMOD
d) SCON

View Answer

Answer: d [Reason:] The registers, accumulator, PSW, B, P0, P1, P2, P3, IP, IE, TCON and SCON are all bit-addressable registers.

4. The higher and lower bytes of a 16-bit register DPTR are represented respectively as
a) LDPTR and HDPTR
b) DPTRL and DPTRH
c) DPH and DPL
d) HDP and LDP

View Answer

Answer: c [Reason:] The registers, DPH and DPL are the higher and lower bytes of a 16-bit register DPTR.

5. The register that is used for accessing external data memory is
a) DPH
b) DPL
c) DPTR
d) NONE

View Answer

Answer: c [Reason:] The Data pointer(DPTR) is used for accessing external data memory which means that it includes both DPH and DPL.

6. Among the four groups of register banks, the number of groups that can be accessed at a time is
a) 1
b) 2
c) 3
d) all the four

View Answer

Answer: a [Reason:] At a time, only one of the four register banks can be accessed.

7. The number of 8-bit registers that a register bank contain is
a) 2
b) 4
c) 6
d) 8

View Answer

Answer: d [Reason:] The 32, 8-bit registers are divided into four groups of 8 registers each, called register banks.

8. If RS1=1, RS0=0, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3

View Answer

Answer: c [Reason:] If RS1=1, RS0=0, then the register bank selected is register bank 2.

9. If RS1=1, RS0=1, then the register bank selected is
a) register bank 0
b) register bank 1
c) register bank 2
d) register bank 3

View Answer

Answer: d [Reason:] If RS1=1, RS0=1, then the register bank selected is register bank 3. If RS1=0, RS0=0, then selected bank is register bank 0.

10. The PCON register consists of
a) power mode bit
b) power idle bit
c) power ideal bit
d) power down bit and idle bit

View Answer

Answer: d [Reason:] The power control register, PCON consists of power down bit and idle bit which activate the power down mode and idle mode in 80C51BH.

11. The on-chip oscillator is stopped in
a) power mode
b) power down mode
c) idle mode
d) ideal mode

View Answer

Answer: b [Reason:] In power down mode, the on-chip oscillator is stopped.

12. In idle mode, the device that is disabled is
a) serial port
b) timer block
c) clock to CPU
d) all of the mentioned

View Answer

Answer: c [Reason:] In idle mode, the oscillator continues to run and the interrupt, serial port and timer blocks are active but the clock to the CPU is disabled.

13. The only way to terminate the power down mode is to
a) CLEAR
b) RESET
c) HOLD
d) HLT

View Answer

Answer: b [Reason:] The only way to terminate the power down mode is hardware reset. The reset redefines all the SFRs but the RAM contents are left unchanged.

14. The idle mode can be terminated by
a) PRESET
b) CLEAR
c) Interrupt
d) Interrupt or reset

View Answer

Answer: d [Reason:] The idle mode can be terminated with a hardware interrupt or hardware reset signal.

Interview MCQ Set 3

1. The 80286 is able to address the physical memory of
a) 8 MB
b) 16 MB
c) 24 MB
d) 64 MB

View Answer

Answer: b [Reason:] The 80286 with its 24-bit address bus is able to address 16 Mbytes of physical memory.

2. The 80286 is able to operate with the clock frequency of
a) 12.5 MHz
b) 10 MHz
c) 8 MHz
d) all of the mentioned

View Answer

Answer: d [Reason:] Various versions of 80286 are available that run on 12.5 MHz, 10 MHz and 8 MHz clock frequencies.

3. The management of the memory system required to ensure the smooth execution of the running process is done by
a) control unit
b) memory
c) memory management unit
d) bus interface unit

View Answer

Answer: c [Reason:] The memory management which is an important task of the operating system is now supported by a hardware unit called memory management unit.

4. The fetching of program from secondary memory to place it in physical memory, during the execution of CPU is called
a) mapping
b) swapping in
c) swapping out
d) pipe lining

View Answer

Answer: b [Reason:] Whenever the portion of a program is required for execution by the CPU, it is fetched from the secondary memory and placed in the physical memory. This is called swapping in of the program.

5. The process of making the physical memory free by storing the portion of program and partial results in the secondary storage called
a) mapping
b) swapping in
c) swapping out
d) pipe lining

View Answer

Answer: c [Reason:] In swapping out, a portion of the program or important partial results required for further execution, may be saved back on secondary storage to make the physical memory free, for further execution of another required portion of the program.

6. The memory that is considered as a large logical memory space, that is not available physically is
a) logical memory
b) auxilary memory
c) imaginary memory
d) virtual memory

View Answer

Answer: d [Reason:] To the user, there exists a very large logical memory space, which is actually not available called virtual memory. This does not exist physically in a system. It is however, possible to map a large virtual memory space onto the real physical memory.

7. Memory management deals with
a) data protection
b) unauthorized access prevention
c) segmented memory
d) all of the mentioned

View Answer

Answer: d [Reason:] The important aspects of memory management are data protection, unauthorized access prevention, and segmented memory.

8. The memory management and protection mechanisms are disabled when the 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned

View Answer

Answer: b [Reason:] In real address mode of 80286, all the memory management and protection mechanisms are disabled.

9. The memory management and protection mechanisms are enabled with advanced instruction set when 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned

View Answer

Answer: c [Reason:] In virtual address mode, 80286 works with all of its memory management and protection capabilities, with the advanced instruction set.

10. The 80286 is an upward object code compatible with 8086 or 8088 when operated in
a) normal mode
b) real address mode
c) virtual address mode
d) real and virtual address mode

View Answer

Answer: d [Reason:] The 80286 is operated in two modes, namely real address mode and virtual address mode. In both the modes, the 80286 is compatible with 8086/8088.

Interview MCQ Set 4

1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned

View Answer

Answer: d [Reason:] The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.

2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines

View Answer

Answer: c [Reason:] The 80386, with its 32-bit address bus, can address up to 4 GB of physical memory.

3. The number of debug registers that are available in 80386, for hardware debugging and control is
a) 2
b) 4
c) 8
d) 16

View Answer

Answer: c [Reason:] The 80386 offers a set of total eight debug registers DR0-DR7, for hardware debugging and control.

4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned

View Answer

Answer: d [Reason:] The memory management section of 80386 supports the virtual memory, paging and four levels of protection, maintaining full compatibility with 80286.

5. The 80386 enables itself to organize the available physical memory into pages, which is known as
a) segmentation
b) paging
c) memory division
d) none of the mentioned

View Answer

Answer: b [Reason:] The concept of paging which is introduced in 80386, enables it to organise the available physical memory into pages of size 4 KB each, under the segmented memory.

6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned

View Answer

Answer: d [Reason:] The 80386 has on-chip address translation cache, and instruction set is upward compatible with all its predecessors.

7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin

View Answer

Answer: c [Reason:] The 80386DX is available in a 132-pin grid array package.

8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned

View Answer

Answer: b [Reason:] The operating frequency of 80386DX is 20MHz and 33 MHz.

9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387

View Answer

Answer: a [Reason:] The 80386 can run the applications under protected mode, in its virtual 8086 mode of operation.

10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086

View Answer

Answer: d [Reason:] The 80386 in protected mode, supports all software written for 8086 and 80286 (to be executed under the control of memory management and protection abilities of 80386).

Interview MCQ Set 5

1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granulary bit

View Answer

Answer: b [Reason:] The accessed bit or attribute bit (A) indicates whether the segment has been accessed by the CPU or not.

2. The TYPE field of descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none

View Answer

Answer: c [Reason:] The type field decides the descriptor type and hence the segment type.

3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned

View Answer

Answer: c [Reason:] If S=0, then system descriptor. If S=1, then code or data segment descriptor.

4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit

View Answer

Answer: d [Reason:] The granularity bit indicates whether the segment is page addressable.

5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit

View Answer

Answer: c [Reason:] If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand segment.

6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned

View Answer

Answer: d [Reason:] The segment descriptors are 8-byte quantities containing access right or attribute bits along with the base and limit of the segments.

7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none

View Answer

Answer: d [Reason:] The five types of segment descriptors of 80386 are: 1. Code or data segment descriptors 2. System descriptors 3. Local descriptors 4. TSS(task state segment) descriptors 5. Gate descriptors.

8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits

View Answer

Answer: d [Reason:] The limit field of the descriptor is of 20 bits.

9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address

View Answer

Answer: c [Reason:] The base address that marks the starting address of the segment in physical memory is decided by the operating system and is of 32 bits.

10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K

View Answer

Answer: d [Reason:] 80386 can handle total 16K descriptors and hence segments.