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Interview MCQ Set 1

1. The disadvantage of machine level programming is
a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned

View Answer

Answer: d [Reason:] The machine level programming is complicated.

2. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file

View Answer

Answer: b [Reason:] .OBJ file is created with same name as source file and extension .OBJ. It contains the coded object modules of the program to be assembled.

3. The advantages of assembly level programming is
a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned

View Answer

Answer: d [Reason:] The assembly level programming is more advantageous than the machine level programming.

4. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM

View Answer

Answer: c [Reason:] All the files should have the extension, .ASM.

5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned

View Answer

Answer: d [Reason:] Before starting the process of entering a small program on PC, ensure that all the files namely Norton’s editor, assembler, linker and debugger are available in the same directory in which work is been done.

6. The listing file is identified by
a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST

View Answer

Answer: d [Reason:] The listing file is automatically generated in the assembly process and is identified by the entered or source file name and an extension .LST.

7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file

View Answer

Answer: a [Reason:] The .OBJ extension is a must for a file to be accepted by the LINK as a valid object file.

8. The listing file contains
a) total offset map of source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned

View Answer

Answer: d [Reason:] The listing file contains total offset map of source file including labels, offset addresses, opcodes, memory allotments for different directives and labels and relocation information.

9. DEBUG.COM facilitates the
a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling

View Answer

Answer: c [Reason:] DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.

10. DEBUG is able to troubleshoot only
a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file

View Answer

Answer: a [Reason:] The DEBUG may be used either to debug a source program or to observe the results of execution of an .EXE file.

Interview MCQ Set 2

1. The procedure of fetching the chosen program segments or data from the secondary storage into the physical memory is
a) mapping
b) swapping
c) unswapping
d) pipe lining

View Answer

Answer: b [Reason:] Swapping is the procedure of fetching the chosen program segments or data from the secondary storage into the physical memory.

2. The procedure of storing back the partial results on to the secondary storage is called
a) mapping
b) swapping
c) unswapping
d) pipe lining

View Answer

Answer: c [Reason:] The procedure of storing back the partial results or data back on to the secondary storage is called unswapping.

3. The ability of 80286 to address the virtual memory per task is
a) 1MB
b) 1GB
c) 1TB
d) none of the mentioned

View Answer

Answer: b [Reason:] The 80286 is able to address 1Gbyte of virtual memory per task.

4. The branch instructions are handled by
a) swapping mechanism
b) unswapping mechanism
c) operating system
d) all of the mentioned

View Answer

Answer: d [Reason:] The handling of branch instructions like JUMP and CALL is taken care of, by the swapping and unswapping mechanism, and operating system.

5. A descriptor contains information of
a) program segment
b) page
c) regarding segment and its access rights
d) all of the mentioned

View Answer

Answer: d [Reason:] The segments or pages have been associated with a data structure known as a descriptor. The descriptor contains information of the page, and also carry relevant information regarding a segment, and its access rights.

6. The descriptors that are used for subroutines and interrupt service routines are
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors

View Answer

Answer: b [Reason:] For data segment, the corresponding descriptor may be data segment descriptor and for code segment there may be code segment descriptor. For subroutines and interrupt service routines there are gate descriptors.

7. A segment with low privilege level is not allowed to access another segment of
a) low privilege level
b) high privilege level
c) low and high privilege level
d) none of the mentioned

View Answer

Answer: b [Reason:] A segment with low privilege level is not allowed to access another segment with high privilege level.

8. A descriptor is used to carry out
a) transfer of control
b) task switching
c) to store privilege level and segment limit
d) all of the mentioned

View Answer

Answer: d [Reason:] A descriptor is used to carry out additional functions like transfer of control and task switching.

9. The descriptor that is used for special system data segments, and control transfer operations is
a) data segment descriptors
b) gate descriptors
c) code segment descriptors
d) system segment descriptors

View Answer

Answer: d [Reason:] The 80286 has system segment descriptor, that is used for special system data segments, and control transfer operations.

10. A code segment descriptor contains
a) 16-bit segment limit
b) 24-bit segment base address
c) 8-bit access rights byte
d) all of the mentioned

View Answer

Answer: d [Reason:] A code or data segment descriptor contains 16-bit segment limit, 24-bit segment base address, 8-bit access rights byte and the remaining 16-bits are reserved by Intel for upward compatibility.

11. In access rights byte, if P (Present)=1, then the segment is mapped into
a) physical memory
b) virtual memory
c) no mapping takes place
d) none of the mentioned

View Answer

Answer: a [Reason:] If P=1, then the segment is mapped into physical memory.

12. In access rights byte, to select system segment descriptor, the condition is
a) S=1
b) S=0
c) S not equal to zero
d) none of the mentioned

View Answer

Answer: b [Reason:] If S (segment descriptor)=0, then system segment descriptor or gate descriptor is selected.

13. If S (segment descriptor)=1, then the descriptor selected is
a) code segment descriptor
b) data segment descriptor
c) stack segment descriptor
d) all of the mentioned

View Answer

Answer: d [Reason:] If S=1, then code or data (including stack) segment descriptors are selected.

14. The memory of limit field is
a) 2 bits
b) 4 bits
c) 8 bits
d) 16 bits

View Answer

Answer: d [Reason:] The limit field, which is the maximum allowed offset address, is of 16 bits.

Interview MCQ Set 3

1. The mechanism to provide protection, that is accomplished with the help of read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations

View Answer

Answer: a [Reason:] The restricted use of segments is accomplished with the help of read/write privileges.

2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned

View Answer

Answer: c [Reason:] In restricted use of segments i.e. segment load check, the segment usages are restricted by classifying the corresponding descriptors, under LDT and GDT.

3. The mechanism that is accomplished using descriptor usages limitations, and rules of privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned

View Answer

Answer: b [Reason:] Restricted accesses to segment, also called, operation reference check, is accomplished using descriptor usages limitations, and rules of privilege check.

4. The mechanism that is executed at certain privilege levels, determined by CPL (Current Privilege Level) and I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned

View Answer

Answer: c [Reason:] The privileged instructions or operations, also called, privileged instruction check, is executed at certain privilege levels, determined by CPL and I/O privilege level(IOPL), as defined by the flag register.

5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned

View Answer

Answer: c [Reason:] The IRET and POPF instructions do not perform any of their functions, if CPL is not of the required privilege level.

6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF

View Answer

Answer: c [Reason:] IF remains unaffected, if CPL is greater than zero. No exception is generated for this condition.

7. The condition, “CPL not equals to zero” satisfies, when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned

View Answer

Answer: d [Reason:] The condition, “CPL not equals to zero” satisfies, when executing the instructions, LIDT, LGDT, LTR, LMSW, CTS and HLT.

8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned

View Answer

Answer: c [Reason:] The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS, OUT, STI, CLI and LOCK.

9. The instruction at which the exception is generated, but the processor extension registers contain the address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC

View Answer

Answer: d [Reason:] At the ESC instruction, the exception is generated, but the processor extension registers contain the address of failing instruction.

10. The exception that has no error code on stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun

View Answer

Answer: b [Reason:] The processor extension segment overrun has no error code on stack.

11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned

View Answer

Answer: d [Reason:] Double exception detected, invalid task state segment, stack segment overrun, processor extension segment overrun, are the protected mode exceptions.

Interview MCQ Set 4

1. The instructions available in the 80386 that are not available in its real address mode is
a) addressing techniques
b) instructions for protected address mode
c) instructions for interrupt handling
d) all of the mentioned

View Answer

Answer: b [Reason:] All the instructions of 80386 are available in this mode except for those designed to work with or for protected address mode.

2. The unit that is disabled in real address mode is
a) central processing unit
b) memory management unit
c) paging unit
d) bus control unit

View Answer

Answer: c [Reason:] The paging unit is disabled in real address mode.

3. To form a physical memory address, appropriate segment register contents are
a) shifted by left by 4 positions
b) added to 16-bit offset address
c) operated using one of addressing modes
d) all of the mentioned

View Answer

Answer: d [Reason:] To form a physical memory address, appropriate segment register contents are shifted by left by 4 positions and then added to 16-bit offset address formed using one of addressing modes, in same way as in the 80386 real address mode.

4. The segments in 80386 real mode are
a) overlapped
b) non-overlapped
c) either overlapped or non-overlapped
d) none of the mentioned

View Answer

Answer: c [Reason:] The segments in 80386 real mode are may be overlapped or non-overlapped.

5. The operation that can be performed on segments in 80386 real mode is
a) read
b) write
c) execute
d) all of the mentioned

View Answer

Answer: d [Reason:] The segments in 80386 real mode can be read, written or executed, i.e. no protection is available.

6. The selectors contain the segment’s
a) segment limit
b) base address
c) access rights byte
d) all of the mentioned

View Answer

Answer: d [Reason:] In protected mode, the contents of segment registers are used as selectors to address descriptors which contain the segment limit, base address and access rights byte of the segment.

7. The linear address is calculated by
a) effective address + segment base address
b) effective address – segment base address
c) effective address + physical address
d) effective address – physical address

View Answer

Answer: a [Reason:] The effective address(offset) is added with segment base address to calculate linear address.

8. If the paging unit is enabled, then it converts linear address into
a) effective address
b) physical address
c) segment base address
d) none of the mentioned

View Answer

Answer: b [Reason:] The paging unit when enabled, it converts linear address into physical address.

9. If the paging unit is disabled, then the linear address is used as
a) effective address
b) physical address
c) segment base address
d) none of the mentioned

View Answer

Answer: b [Reason:] The linear address is used as physical address if the paging unit is disabled.

10. The paging unit is enabled only in
a) virtual mode
b) addressing mode
c) protected mode
d) none of the mentioned

View Answer

Answer: c [Reason:] The paging unit is enabled only in protected mode.

11. For a single task in protected mode, the 80386 can address the virtual memory of
a) 32 GB
b) 64 MB
c) 32 TB
d) 64 TB

View Answer

Answer: d [Reason:] In protected mode, the 80386 can address 4 GB of physical memory and 64 TB of virtual memory per task.

Interview MCQ Set 5

1. The 80286 CPU acts just as that of 8086 when operated in
a) real addressing mode
b) protected virtual address mode
c) real and protected virtual address modes
d) none of the mentioned

View Answer

Answer: a [Reason:] In the real addressing mode of operation of 80286, it just acts as a fast 8086.

2. In real addressing mode, the 80286 addresses a physical memory of
a) 16 MB
b) 8 MB
c) 2 MB
d) 1 MB

View Answer

Answer: d [Reason:] In real addressing mode, the 80286 addresses a physical memory of 1 Mbytes using A0-A19. The lines A20-A23 are not used by the internal circuit of 80286 in this mode.

3. In real addressing mode, the 80286 operates at a speed
a) faster than that of 8086
b) half of that of 8086
c) slower than that of 8086
d) same as that of 8086

View Answer

Answer: a [Reason:] Because of extra pipelining and other circuit level improvements, in real address mode also, the 80286 operates at a much faster rate than 8086.

4. In physical memory, if the segment size limit is exceeded by the instruction or data then
a) instruction is not executed
b) exception is generated
c) saves to next segment automatically
d) none of the mentioned

View Answer

Answer: b [Reason:] An exception is generated, if the segment size limit is exceeded by the instruction or the data.

5. The 80286 reserves fixed area of physical memory for
a) system initialization
b) interrupt vector table
c) system initialization and interrupt vector table
d) none of the mentioned

View Answer

Answer: c [Reason:] The 80286 reserves two fixed areas of physical memory for system initialization and interrupt vector table.

6. In the real mode, the memory that is reserved for interrupt vector table is
a) first 2 KB of memory
b) first 1 KB of memory
c) last 2 KB of memory
d) last 1 KB of memory

View Answer

Answer: b [Reason:] In the real mode, the first 1 Kbyte of memory starting from the address 00000H to 003FFH, is reserved for interrupt vector table.

7. In the real mode, the memory that is reserved for system initialization is
a) from 004FFH to 0FFFFH
b) from 004FFH to 05FFFH
c) from FFFF0H to FFFFFH
d) from FFF00H to FFFFFH

View Answer

Answer: c [Reason:] The addresses from FFFF0H to FFFFFH are reserved for system initialization, in real addressing mode.

8. When 80286 is reset, it always starts its execution in
a) protected virtual addressing mode
b) real addressing mode
c) either real or protected virtual address modes
d) none of the mentioned

View Answer

Answer: b [Reason:] When 80286 is reset, it always starts its execution in real addressing mode.

9. The 80286 in real addressing mode performs
a) initialization of IP
b) enables interrupts
c) sets up descriptor table
d) all of the mentioned

View Answer

Answer: d [Reason:] The 80286 in real addressing mode performs the following functions: it initializes IP and other registers of 80286, initializes the peripheral, enables interrupts, sets up descriptor tables, and then prepares it for entering the protected virtual address mode.

10. In real address mode, while addressing the physical memory, the 80286 uses the signal
a) HLDA
b) BHE (active low)
c) CAP
d) HOLD

View Answer

Answer: b [Reason:] In real address mode, while addressing the physical memory, the 80286 uses BHE (active low) along with A0-A19.