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Interview MCQ Set 1

1. By using privilege mechanism the protection from unauthorised accesses is done to
a) operating system
b) interrupt handlers
c) system softwares
d) all of the mentioned

View Answer

Answer: d [Reason:] The operating system, interrupt handlers and other system softwares can be protected from unauthorised accesses in virtual address space of each task using the privilege mechanism.

2. The task privilege level at the instant of execution is called
a) Descriptor privilege level (DPL)
b) Current privilege level (CPL)
c) Effective privilege level (EPL)
d) None of the mentioned

View Answer

Answer: b [Reason:] Any one of the four privilege levels may be used to execute a task. The task privilege level at that instant is called the Current Privilege Level (CPL).

3. Once the CPL is selected, it can be changed by
a) hold
b) transferring control using system descriptors
c) transferring control using gate descriptors
d) transferring control using interrupt descriptors

View Answer

Answer: c [Reason:] Once the CPL is selected, it cannot be changed during the execution normally in a single code segment. It can only be changed by transferring the control, using gate descriptors, to a new segment.

4. The data segments defined in GDT (global descriptor table) and the LDT (local descriptor table) can be accessed by a task with
a) privilege level 0
b) privilege level 1
c) privilege level 2
d) privilege level 3

View Answer

Answer: a [Reason:] A task executing at level 0, the most privilege level, can access all the data segments defined in GDT and the LDT of the task.

5. A task with privilege level 0, doesnot refer to all the lower level privilege descriptors in
a) GDT (global descriptor table)
b) LDT (local descriptor table)
c) IDT (interrupt descriptor table)
d) None of the mentioned

View Answer

Answer: b [Reason:] The task with privilege level 0, refers to all the lower level privilege descriptors which applies to all the descriptors except the LDT descriptors.

6. The selector RPL that uses a less trusted privilege than the current privilege level for further use is known as
a) Least task privilege level
b) Descriptor privilege level
c) Effective privilege level
d) None of the mentioned

View Answer

Answer: c [Reason:] A selector RPL uses a less trusted privilege than the current privilege level for further use. This is known as the Effective Privilege Level of the task.

7. The effective privilege level is
a) maximum numeric of RPL and CPL
b) minimum privilege of RPL and CPL
c) numeric minimum and privilege maximum of RPL and CPL
d) none of the mentioned

View Answer

Answer: c [Reason:] The effective privilege level is minimum in numeric and maximum in privilege of RPL and CPL.

8. The task requesting an access to a descriptor is allowed to access after checking the
a) type of descriptor
b) privilege level
c) type of descriptor and privilege level
d) corresponding segment

View Answer

Answer: c [Reason:] The task requesting an access to a descriptor is allowed to access to it and to the corresponding segment, only after checking type of the descriptor and privilege level(CPL, RPL, DPL).

9. A CALL instruction can reference only a code segment descriptor with
a) DPL less privilege than CPL
b) DPL equal privilege to CPL
c) DPL greater privilege than CPL
d) All of the mentioned

View Answer

Answer: b [Reason:] A CALL or JUMP instruction can reference only a code segment descriptor with DPL equal to CPL of the task or a segment with a DPL of equal or greater privilege than CPL.

10. The RPL of a selector that referred to the code descriptor must have
a) less privilege than CPL
b) greater privilege than CPL
c) equal privilege than CPL
d) any privilege regarding CPL

View Answer

Answer: c [Reason:] The RPL of a selector that referred to the code descriptor must have the same privilege as CPL.

11. The instruction that refers to only code segment descriptors with DPL equal to or less than the task CPL is
a) CALL
b) IRET
c) ESC
d) RET and IRET

View Answer

Answer: d [Reason:] The RET and IRET instructions are to refer to only code segment descriptors with DPL equal to or less than the task CPL.

12. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must be
a) equally privileged as CPL
b) greater or equally privileged than CPL
c) less or equally privileged than CPL
d) less privileged than CPL

View Answer

Answer: c [Reason:] When a CALL or JUMP instruction references a Task State Segment(TSS) descriptor, then DPL must be less or equally privileged than CPL.

13. The data segment access refers to
a) loading DS
b) loading ES
c) loading SS
d) all of the mentioned

View Answer

Answer: d [Reason:] Loading DS, ES or SS for referring to a new descriptor comes under the data segment access.

14. An exception is generated when
a) privilege test is negative
b) an improper segment is referenced
c) referenced segment is not present in physical memory
d) all of the mentioned

View Answer

Answer: d [Reason:] If the privilege test is negative or an improper segment is referenced then an exception 13 is generated. If the referenced segment is not present in physical memory, an exception 11 is generated.

Interview MCQ Set 2

1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex

View Answer

Answer: c [Reason:] Basically, there are three modes of data transmission. simplex, duplex and half duplex.

2. If the data is transmitted only in one direction over a single communication channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

View Answer

Answer: a [Reason:] In simplex mode, the data transmission is unidirectional. For example, a CPU may transmit data for a CRT display unit in this mode.

3. If the data transmission takes place in either direction, but at a time data may be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode

View Answer

Answer: d [Reason:] In half duplex mode, data transmission is bidirectional but not at a time. For example, Walkie-Talkie.

4. In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)

View Answer

Answer: a [Reason:] Transmitter Clock Input (TXC(active low)) is a pin that controls the rate at which the character is to be transmitted.

5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned

View Answer

Answer: d [Reason:] Transmitted Data Output pin carries serial stream of the transmitted data bits along with other information like start bits, stop bits and parity bits etc.

6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)

View Answer

Answer: b [Reason:] RXRDY(Receiver ready output) may be used either to interrupt the CPU or polled by the CPU.

7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned

View Answer

Answer: d [Reason:] RS232C has been used for long and has a few disadvantages like limited speed of communication, high-voltage level signaling and big-size communication adapters.

8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned

View Answer

Answer: d [Reason:] The USB standards support the signaling rates. Also, USB signaling is implemented in differential in low- and full-speed options.

9. The bit packet that commands the device either to receive data or transmit data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet

View Answer

Answer: b [Reason:] The token packet is a second type of packet which commands the device either to receive data or transmit data.

10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet

View Answer

Answer: c [Reason:] PRE packets are only of importance to low-speed USB devices.

Interview MCQ Set 3

1. The block of 8237 that decodes the various commands given to the 8237 by the CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

View Answer

Answer: b [Reason:] The program control block decodes various commands given to the 8237 by the CPU before servicing a DMA request.

2. The priority between the DMA channels requesting the services can be resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned

View Answer

Answer: c [Reason:] The priority encoder block resolves the priority between the DMA channels requesting the services.

3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register

View Answer

Answer: b [Reason:] The current address register holds the current memory address. The current address register is accessed during the DMA transfer.

4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register

View Answer

Answer: a [Reason:] The current word register is a 16-bit register that holds the data transfers. The word count is decremented after each transfer, and the new value is stored again in the register.

5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated

View Answer

Answer: c [Reason:] When the count becomes zero, the EOP signal is generated. This can be written in successive bytes by the CPU, in program mode.

6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned

View Answer

Answer: b [Reason:] The current address register is byte-wise programmed by the CPU, i.e. lower byte first and the higher byte later.

7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
b) current address register
c) base address register
d) command register

View Answer

Answer: c [Reason:] The contents of base address register cannot be read by the CPU. These contents are used internally for auto-initialization.

8. The register that maintain an original copy of the respective initial current address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register

View Answer

Answer: b [Reason:] The base address register maintains an original copy of current address register and current word register, before incrementing or decrementing.

9. The register that can be automatically incremented or decremented, after each DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register

View Answer

Answer: d [Reason:] The address is automatically incremented or decremented after each DMA transfer, and the resulting address value is again stored in the current address register.

10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned

View Answer

Answer: d [Reason:] Memory read, memory write and verify transfer are the three types of DMA transfer.

Interview MCQ Set 4

1. The number of hardware interrupts that the processor 8085 consists of is
a) 1
b) 3
c) 5
d) 7

View Answer

Answer: c [Reason:] The processor 8085 has five hardware interrupt pins. Out of these five, four pins were alloted fixed vector addresses but the pin INTR was not alloted by vector address, rather an external device was supposed to hand over the type of the interrupt to the microprocessor.

2. The register that stores all the interrupt requests in it in order to serve them one by one on priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register

View Answer

Answer: a [Reason:] The interrupts at IRQ input lines are handled by Interrupt Request Register internally.

3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None

View Answer

Answer: c [Reason:] Also, Interrupt Mask Register operates on IRR(Interrupt Request Register) at the direction of the Priority Resolver.

4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned

View Answer

Answer: d [Reason:] The interrupt control logic performs all the operations that are involved within the interrupts like accepting and managing interrupt acknowledge signals, interrupts.

5. In cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b) 8
c) 16
d) 64

View Answer

Answer: d [Reason:] A single 8259A provides 8 vectored interrupts. In cascade mode, 64 vectored interrupts can be provided.

6. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none

View Answer

Answer: b [Reason:] When the pin is used in buffered mode, then it can be used as a buffer enable to control buffer transreceivers. If it is not used in buffered mode, then the pin is used as input to designate whether the chip is used as a master or a slave.

7. Once the ICW1 is loaded, then the initialisation procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned

View Answer

Answer: d [Reason:] The initialisation procedure involves i) edge sense circuit is reset. ii) IMR is cleared. iii) IR7 input is assigned the lowest priority. iv) slave mode address is set to 7 v) special mask mode is cleared and the status read is set to IRR.

8. When non-specific EOI command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR

View Answer

Answer: b [Reason:] When non-specific EOI command is issued to 8259A it will automatically reset the highest ISR.

9. In the application where all the interrupting devices are of equal priority, the mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI

View Answer

Answer: a [Reason:] The automatic rotation is used in the applications where all the interrupting devices are of equal priority.

Interview MCQ Set 5

1. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] There are three counters that can be used as either counters or delay generators.

2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none

View Answer

Answer: b [Reason:] The control word register can only be written and cannot be read.

3. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3

View Answer

Answer: a [Reason:] Mode 0 is also called as interrupt on terminal count.

4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles

View Answer

Answer: a [Reason:] After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the output becomes high and remains so for (N-1) clock pulses.

5. The generation of square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4

View Answer

Answer: c [Reason:] When the count N loaded is even, then for half of the count, the output remains high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse decrements it by 1 resulting in an even count value.

6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none

View Answer

Answer: b [Reason:] SC denotes select counter.

7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB

View Answer

Answer: c [Reason:] To access 16 bit, first LSB is loaded first, and then MSB.

8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count

View Answer

Answer: b [Reason:] If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.

9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high

View Answer

Answer: b [Reason:] If the GATE signal is enabled, then the counter starts counting.

10. The control word register contents are used for
a) initialising the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned

View Answer

Answer: d [Reason:] The control word register contents are used for i) initialising the operating modes (mode 0-mode 4) ii) selection of counters (counter0-counter2) iii) choosing binary or BCD counters iv) loading of the counter registers.