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Interview MCQ Set 1

1. The unit that executes all the numeric processor instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned

View Answer

Answer: c [Reason:] The 8087 is divided into two sections namely control unit and numeric extension unit in which the numeric extension unit executes all the numeric processor instructions.

2. The unit that receives and decodes the instructions in 8087 is
a) Control unit
b) ALU
c) Numeric extension unit
d) None of the mentioned

View Answer

Answer: a [Reason:] The control unit receives, decodes the instructions, and executes the 8087 control instructions.

3. The control unit functions in
a) establishing communication between CPU and memory
b) coordinating the internal coprocessor execution
c) reads and writes memory operands
d) all of the mentioned

View Answer

Answer: d [Reason:] The control unit is used for establishing communication between CPU and memory and coordinating the internal coprocessor execution.

4. When the numeric extension unit (NEU) begins its execution, then the signal that is active is
a) BUSY (active high)
b) BUSY (active low)
c) READY (active low)
d) RESET (active high)

View Answer

Answer: a [Reason:] When NEU begins its execution, the BUSY signal is pulled up. Also, this output signal when high, indicates to the CPU that it is busy with the execution of an allotted instruction.

5. The register that allows the register programmer to select the required processing options is
a) significant
b) exponent
c) control word register
d) none of the mentioned

View Answer

Answer: c [Reason:] The control word register allows the register programmer to select the required processing options out of available ones. It is used to control the operation of 8087.

6. Invalid operation is the exception generated due to
a) stack overflow
b) stack underflow
c) indeterminate form as result
d) all of the mentioned

View Answer

Answer: d [Reason:] Invalid operation is generated due to stack overflow, stack underflow, indeterminate form as result, or non-number (NAN) as operand.

7. The exception generated for a too big result to fit in the format is
a) invalid operation
b) overflow
c) denormalised operand
d) result overflow

View Answer

Answer: b [Reason:] A too big result to fit in the format generates this exception. The condition code bits indicate that the result is prohibitively large.

8. If the result is infinity, then the exception generated is
a) overflow
b) invalid operation
c) denormalised operand
d) zero divide

View Answer

Answer: d [Reason:] If any non-zero finite operand is divided by zero, the zero divide exception is generated. The resulting condition code bits indicate that the result is infinity, even if the exception is masked.

9. To operate 8087 in maximum mode, the pin MN/MX (active low) is
a) connected to Vcc or power supply
b) connected to ground
c) left unconnected
d) none of the mentioned

View Answer

Answer: b [Reason:] The 8087 can operate in maximum mode, only when the MN/MX (active low) pin of the CPU is grounded. In maximum mode, all the control signals are derived using a sequence chip known as a bus controller.

10. If the result is rounded according to the rounding control bits, then the exception generated is
a) denormalized operand
b) underflow
c) inexact result
d) invalid operation

View Answer

Answer: c [Reason:] If it is impossible to fit the actual result in the specified format, the result is rounded according to the rounding control bits, and an exception is generated. This sets the precision exception flag.

11. The instruction that stores a copy of top of stack into the memory, and pops the top of the stack is
a) FST
b) FSTP
c) FIST
d) FLD

View Answer

Answer: b [Reason:] FSTP (store floating point number and pop) stores a copy of top of stack into memory or any coprocessor register, and then pops the top of the stack.

12. The instruction that multiplies the content of the stack top by 2n is
a) FMUL
b) FPREM
c) FSCAL
d) FCSH

View Answer

Answer: c [Reason:] FSCAL instruction multiplies the content of the stack top by 2n, where n is the integral part of stack and stores the result in stack.

13. If the opcode bit is D=1, then the source and destination operands are
a) incremented
b) decremented
c) cleared
d) interchanged

View Answer

Answer: d [Reason:] If D=1, then it interchanges the source and destination operands.

Interview MCQ Set 2

1. The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned

View Answer

Answer: d [Reason:] The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time. Only a few pages of the segments, which are required currently for the execution, need to be available in the physical memory.

2. The size of the pages in paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none

View Answer

Answer: b [Reason:] The paging divides the memory into fixed size pages.

3. To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism

View Answer

Answer: d [Reason:] The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses provided by segmentation unit, into physical addresses.

4. The control register that stores the 32-bit linear address, at which the previous page fault is detected is
a) CR0
b) CR1
c) CR2
d) CR3

View Answer

Answer: c [Reason:] The control register, CR2, is used to store the 32-bit linear address, at which the previous page fault is detected.

5. Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page

View Answer

Answer: b [Reason:] The paging unit handles every task in terms of three components namely page directory, page table and the page itself.

6. The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3

View Answer

Answer: d [Reason:] The control register, CR3, is used as page directory physical base address register, to store the physical starting address of the page directory.

7. The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits

View Answer

Answer: d [Reason:] The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.

8. Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes

View Answer

Answer: b [Reason:] Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.

9. The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes

View Answer

Answer: c [Reason:] Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.

10. The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned

View Answer

Answer: a [Reason:] The dirty bit (D) is set before a write operation to the page is carried out.

11. The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned

View Answer

Answer: c [Reason:] The D-bit is undefined for page directory entries.

12. The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned

View Answer

Answer: d [Reason:] The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.

13. The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned

View Answer

Answer: c [Reason:] To optimize the considerable time taken for conversion, a page table cache is provided, which stores the 32 recently accessed page table entries.

14. The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned

View Answer

Answer: c [Reason:] The page table cache is also known as translation look aside buffer.

Interview MCQ Set 3

1. The instructions that pass through the fetch, decode and execution stages sequentially is known as
a) sequential instruction
b) sequence of fetch, decode and execution
c) linear instruction sequencing
d) non-linear instruction sequencing

View Answer

Answer: c [Reason:] The linear instruction sequencing is the one in which the instructions that pass through the fetch, decode and execution stages sequentially.

2. During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
a) control unit
b) bus interface unit
c) execution unit
d) cpu

View Answer

Answer: b [Reason:] During the execution of instructions, only after the bus interface unit of CPU reads the data from the main memory and returns it to the register, the next instruction execution will commence.

3. Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] Pentium’s superscalar architecture employs five stage pipeline with U and V pipes. Thus it can execute two instructions per clock.

4. The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction

View Answer

Answer: a [Reason:] The speculative execution is an execution which means that the CPU should speculate which of the next instructions can be executed earlier.

5. The execution in which the consecutive instruction execution in a sequential flow is hampered is
a) speculative execution
b) out of turn execution
c) dual independent bus
d) multiple branch prediction

View Answer

Answer: b [Reason:] In the out of turn execution, the consecutive instruction execution in a sequential flow is hampered and the CPU should be able to execute out of turn instructions.

6. A dual independent bus has
a) Enhanced system bandwidth
b) CPU that can access both cache and memory simultaneously
c) High throughput
d) All of the mentioned

View Answer

Answer: d [Reason:] A dual independent bus architecture is incorporated by Pentium-Pro to get an enhanced system bandwidth and it also yields high throughput. It has the CPU which can access both main memory and the cache simultaneously.

7. The unit that is used to implement the multiple branch prediction in Pentium-Pro is
a) control unit
b) bus interface unit
c) branch target buffer
d) branch instruction register

View Answer

Answer: c [Reason:] The processor uses an associative memory called branch target buffer for implementing the algorithm, multiple branch prediction.

8. Which of the following is not an independent engine of Pentium-Pro?
a) fetch-decode unit
b) dispatch-execute unit
c) control-execute unit
d) retire unit

View Answer

Answer: c [Reason:] Pentium-Pro incorporates three independent engines, 1. Fetch-decode unit 2. Dispatch-execute unit 3. Retire unit.

9. The unit that accepts the sequence of instructions from the instruction cache as input is
a) fetch-decode unit
b) dispatch-execute unit
c) retire unit
d) none

View Answer

Answer: a [Reason:] The fetch-decode unit accepts the sequence of instructions from the instruction cache as input and then decodes them.

10. In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] A set of three parallel decoders accepts the stream of fetched instructions and decode them.

Interview MCQ Set 4

1. Programmable peripheral input-output port is other name for
a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port

View Answer

Answer: b [Reason:] The parallel input-output port chip 8255 is also known as programmable peripheral input-output port.

2. Port C of 8255 can function independently as
a) input port
b) output port
c) either input or output ports
d) both input and output ports

View Answer

Answer: c [Reason:] Port C can function independently either as input or as output ports.

3. All the functions of the ports of 8255 are achieved by programming the bits of an internal register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned

View Answer

Answer: c [Reason:] By programming the bits of control word register, the operations of the ports are specified.

4. The data bus buffer is controlled by
a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned

View Answer

Answer: b [Reason:] The data bus buffer is controlled by read/write control logic.

5. The input provided by the microprocessor to the read/write control logic is
a) RESET
b) A1
c) WR(ACTIVE LOW)
d) All of the mentioned

View Answer

Answer: d [Reason:] RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs provided by the microprocessor to the read/write control logic of 8255.

6. The device that receives or transmits data upon the execution of input or output instructions by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned

View Answer

Answer: c [Reason:] 3-state bidirectional buffer is used to receives or transmits data upon the execution of input or output instructions by the microprocessor.

7. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper

View Answer

Answer: d [Reason:] Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

8. If A1=0, A0=1 then the input read cycle is performed from
a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus

View Answer

Answer: b [Reason:] If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

9. The function, ‘data bus tristated’ is performed when
a) CS(active low) =1
b) CS(active low) =0
c) CS(active low) =0, RD(active low) =1, WR(active low) =1
d) CS(active low) =1 OR CS(active low) =0, RD(active low) =1, WR(active low) =1

View Answer

Answer: d [Reason:] The data bus is tristated when chip select pin=1 or chip select pin=0 and read and write signals are high i.e 1.

10. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK

View Answer

Answer: c [Reason:] If reset pin is enabled then the control word register is cleared.

Interview MCQ Set 5

1. The power control register is
a) used for power saving during idle state
b) used for eventual power off to 8051 chip
c) non-bit addressable register
d) all of the mentioned

View Answer

Answer: d [Reason:] The power control register is used for power saving during idle state of the microcontroller and eventual power off to the microcontroller chip. It has SMOD bit which is used to double the baud rate.

2. The state of signals in idle mode is
a) ALE is high
b) PSEN is high
c) PSEN(active low) is high
d) ALE and PSEN(active low) are high

View Answer

Answer: d [Reason:] ALE and PSEN(active low) remain high in Idle mode.

3. To come out of idle mode, the external interrupt that is enabled is
a) SI(serial)
b) INT0
c) INT1
d) All of the mentioned

View Answer

Answer: d [Reason:] To come out of idle mode, any external interrupt that is enabled like SI(Serial), INT0 and INT1.

4. The microcontroller enters into power down mode when
a) SMOD bit of PCON is set
b) GF1 bit of PCON is set
c) PD bit of PCON is set
d) GF2 bit of PCON is set

View Answer

Answer: c [Reason:] If the PD bit of PCON register is set, it enters power down mode.

5. The clock signal is disabled to all parts of 8051 in
a) normal mode
b) idle mode
c) power down mode
d) addressing mode

View Answer

Answer: c [Reason:] In power down mode, the clock signal to all parts of 8051 chip is disabled.

6. During power down to save battery, the supply voltage can be reduced to a value of
a) 4 volts
b) 2 volts
c) 8 volts
d) 1 volt

View Answer

Answer: b [Reason:] The supply voltage can be reduced to a value of around 2 volts, during power down to save battery.

7. The signal that only pulls the microcontroller(8051) out of the power down mode is
a) CLEAR
b) LEAVE
c) RESET
d) EXIT

View Answer

Answer: c [Reason:] Only Reset signal can pull 8051 out of the power down mode.

8. The state of signals in power down mode is
a) ALE is high
b) PSEN is low
c) ALE and PSEN(active low) are high
d) ALE and PSEN(active low) are low

View Answer

Answer: d [Reason:] ALE and PSEN(active low) remain low in power down mode of 8051.

9. In power down mode,
a) Port pins maintain their logic levels
b) SFRs maintain their logic levels
c) Clock signal is disabled
d) All of the mentioned

View Answer

Answer: d [Reason:] In power down mode, the clock signal is disabled and all the port pins and respective SFRs maintain their logic levels.

10. The SMOD bit is used to
a) decrease the baud rate by 2
b) increase the baud rate by 4
c) increase the baud rate by 2
d) triple the baud rate

View Answer

Answer: c [Reason:] The SMOD bit is used to double the baud rate.