Generic selectors
Exact matches only
Search in title
Search in content
Search in posts
Search in pages
Filter by Categories
nmims post
Objective Type Set
Online MCQ Assignment
Question Solution
Solved Question
Uncategorized

Interview MCQ Set 1

1. If a number of instructions are repeating through the main program, then to reduce the length of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned

View Answer

Answer: c [Reason:] For a certain number of instructions that are repeated in the main program, when macro is defined then the code of program is reduced by placing the name of the macro at which the set of instructions are needed to be repeated.

2. The process of assigning a label or macroname to the string is called
a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro

View Answer

Answer: d [Reason:] The process of assigning label to the string is called defining a macro.

3. A macro within a macro is called
a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned

View Answer

Answer: b [Reason:] A macro may be called from inside a macro. This type of macro is called nested macro.

4. A macro can be defined at
a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program

View Answer

Answer: d [Reason:] A macro can be defined anywhere in a program.

5. A macro can be used as ________
a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned

View Answer

Answer: d [Reason:] A macro may be used in data segment and can also be used to represent statements and directives.

6. The end of a macro can be represented by the directive.
a) END
b) ENDS
c) ENDM
d) ENDD

View Answer

Answer: c [Reason:] The ENDM directive marks the end of the instructions or statements sequence assigned with the macro name.

7. Inserting the statements and instructions represented by macro, directly at the place of the macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned

View Answer

Answer: a [Reason:] Inserting the statements and instructions at the place of macroname, in the program, is known as calling a macro.

8. The time required for execution of a macro is ________ that of procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned

View Answer

Answer: b [Reason:] The time required for execution of a macro is less than that of procedure as it does not contain CALL and RET instructions as the procedures do.

9. Which of the following statements is incorrect?
a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics

View Answer

Answer: c [Reason:] Macro does not require stack memory and hence has less time for execution.

10. The beginning of the macro can be represented as
a) START
b) BEGIN
c) MACRO
d) None of the mentioned

View Answer

Answer: c [Reason:] The beginning of the macro is represented as macroname followed by the directive MACRO. SYNTAX: macroname MACRO EXAMPLE: STRINGS MACRO.

Interview MCQ Set 2

1. The additional instructions that are designed specially for performing multimedia tasks are known as
a) additional MMX instructions
b) multimedia MMX instructions
c) enhanced MMX instructions
d) none of the mentioned

View Answer

Answer: c [Reason:] The MMX technology adds 57 new instructions to the instruction set of processors. These instructions are known as enhanced MMX instructions, and are designed specifically for performing multimedia tasks.

2. The MMX instruction, EMMS consists of __________ on which it operates.
a) source operand
b) destination operand
c) source and destination operand
d) none of the mentioned

View Answer

Answer: d [Reason:] The instruction, EMMS, does not have any operand.

3. In all the MMX instructions, the destination operand resides in
a) Memory
b) RAM
c) Either in an MMX register or in memory
d) MMX register

View Answer

Answer: d [Reason:] In all the MMX instructions, the source operand is found either in an MMX register or in memory, and the destination operand resides in MMX register.

4. For the MMX instructions, the prefix, P, is used to represent the mode of
a) real addressing mode
b) virtual mode
c) packed mode
d) programmable mode

View Answer

Answer: c [Reason:] In the MMX instructions, if the operands are in packed mode, the prefix, P, is used to indicate packed data.

5. For the MMX instructions, the suffix, S, is used to represent
a) status
b) saturation
c) signed saturation
d) unsigned saturation

View Answer

Answer: c [Reason:] For the MMX instructions, the suffix “S” indicates signed saturation, and “US” indicates unsigned saturation, while executing arithmetic computation in saturation mode.

6. The instruction that is used for quadword is
a) PADD
b) PCMPEQ
c) PAND
d) None of the mentioned

View Answer

Answer: d [Reason:] The instructions, PADD, PCMPEQ and PAND are used for packed byte, word and double word.

7. The instruction, PSUBB, performs subtraction in
a) packed word
b) packed byte
c) packed double word
d) unpacked word

View Answer

Answer: b [Reason:] The instruction, PSUBB, performs subtraction in packed byte.

8. The instruction, PCMPGT, is used to compare two data types and check
a) equal to condition
b) less than condition
c) greater than condition
d) equal to and greater than condition

View Answer

Answer: c [Reason:] The instruction, PCMPGT, compares to check the greater than condition in packed bytes, packed words and packed double words.

9. The instruction that is not operated on quad word is
a) MOV
b) PSLL
c) PSRA
d) All of the mentioned

View Answer

Answer: c [Reason:] The instruction, PSRA, performs arithmetic shift, right in a single cycle. It supports only the shifting of packed word and double word data types.

10. When the instruction, PMULLW, is performed, then the lower order 16-bits of the 32 bit products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination

View Answer

Answer: b [Reason:] In the instruction, PMULLW, four 16 X 16 multiplications are performed, and the lower order 16 bits of the 32-bit products are stored in destination.

11. When the instruction, PMULHW, is performed, then the higher order 16-bits of the 32 bit products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination

View Answer

Answer: b [Reason:] In the instruction, PMULHW, four 16 X 16 multiplications are performed, and the higher order 16 bits of the 32-bit products are stored in destination.

12. The instruction in which both multiplication and addition are performed is
a) PAND
b) PMULHW
c) PADD
d) PMADDWD

View Answer

Answer: d [Reason:] PMADDWD is an important multimedia instruction, which multiplies the four signed words of destination operand, with four signed words of source operand. This results in 32-bit double words which are added, and the result is stored in the higher double word of the destination operand.

13. If the result of PCMPEQ, which is a comparison of two packed data types, is a success, then the mask generated is
a) mask 0s
b) mask 1s
c) mask 2s
d) mask 3s

View Answer

Answer: b [Reason:] If the result of PCMPEQ, which is a comparison of two packed data types is a success, then the mask 1s is generated, otherwise a mask of 0s is generated, in destination operand.

Interview MCQ Set 3

1. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports

View Answer

Answer: c [Reason:] In the I/O mode, the 8255 ports work as programmable I/O ports.

2. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports

View Answer

Answer: c [Reason:] In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.

3. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned

View Answer

Answer: d [Reason:] In mode 0, any port can be used as input or output and output ports are latched.

4. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none

View Answer

Answer: b [Reason:] In this mode, the handshaking signals control the input or output action of the specified port.

5. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches

View Answer

Answer: a [Reason:] If the value of the pin STB (Strobe Input) falls to low level, then input port is loaded into input latches.

6. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports

View Answer

Answer: c [Reason:] This signal indicates that the printer is selected.

7. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds

View Answer

Answer: d [Reason:] The pulse width of the signal must be more than 50microseconds at the receiving terminal.

8. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned

View Answer

Answer: d [Reason:] The level of the signal ERROR(active low) becomes ‘low’ when the printer is in Paper end state, Offline state and Error state.

9. The signals that are provided to maintain proper data flow and synchronisation between the data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none

View Answer

Answer: a [Reason:] Handshaking signals maintain proper data flow and synchronisation.

10. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned

View Answer

Answer: d [Reason:] In mode 2 of 8255, single 8-bit port is available i.e group A.

Interview MCQ Set 4

1. The interrupt for which the processor has highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT

View Answer

Answer: c [Reason:] The Non-Maskable Interrupt input pin has the highest priority among all the external interrupts.

2. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT

View Answer

Answer: b [Reason:] TRAP is the internal interrupt that has highest priority among all the interrupts except the Divide By Zero (Type 0) exception.

3. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt

View Answer

Answer: c [Reason:] When NMI is activated, the current instruction being executed is completed and then NMI is served. In case of string instructions, it is served after the complete string is manipulated.

4. The NMI pin should remain high for atleast
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles

View Answer

Answer: d [Reason:] The NMI pin should remain high for atleast 2 clock cycles and need not be synchronized with the clock for being sensed.

5. The INTR signal can be masked by resetting the
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag

View Answer

Answer: b [Reason:] The INTR signal can be masked by resetting the interrupt flag.

6. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged

View Answer

Answer: a [Reason:] The INTR signal must go high in the clock cycle of the current instruction in order to respond in the next instruction cycle.

7. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle

View Answer

Answer: d [Reason:] At the end of each instruction, the status of the pending interrupts is checked.

8. Once the processor responds to an INTR signal, the IF is automatically
a) set
b) reset
c) high
d) low

View Answer

Answer: b [Reason:] The IF is automatically reset when the processor responds to an INTR signal. If the processor wants to respond to any type of INTR signal further then, the IF should again be set.

9. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the start of the next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned

View Answer

Answer: a [Reason:] The pin LOCK (active low) remains low till the start of the next machine cycle.

10. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles

View Answer

Answer: c [Reason:] The INTA (active low) goes low and remains low for two clock cycles before returning back to the high state.

Interview MCQ Set 5

1. The first processor with an inbuilt floating point unit is
a) 80386
b) 80486
c) 80286
d) 8086

View Answer

Answer: b [Reason:] The 32-bit CPU 80486 from Intel is the first processor with an inbuilt floating point unit. 80486DX is the first CPU with an on chip floating point unit.

2. Which of the following signal is handled by bus control and request sequencer?
a) ADS#
b) PWT
c) RDY#
d) All of the mentioned

View Answer

Answer: d [Reason:] The bus control and request sequencer handles the signals like ADS#, PWT, RDY#, W/R#, INTR, NMI, LOCK#, HOLD, HLDA, RESET and M/IO# which basically controls the bus access and operations.

3. The unit that subjects the processor operation to boundary scan tests is
a) parity generation and control unit
b) prefetcher unit
c) boundary scan and control unit
d) segmentation unit

View Answer

Answer: c [Reason:] The boundary scan and control unit subjects the processor operation to boundary scan tests to ensure the correct operation of various components of the mother board.

4. The management of virtual memory of the system and adequate protection to data or codes in the physical memory is provided by
a) segmentation unit
b) paging unit
c) attribute PLA
d) all of the mentioned

View Answer

Answer: d [Reason:] The segmentation unit, paging unit, attribute PLA, descriptor registers, translation look aside buffer and limit work together to manage the virtual memory of the system and provide the adequate protection to the codes or data in the physical memory.

5. The flag that is added to 80486 in additional to the flags similar to 80386 is
a) alignment check flag
b) parity check flag
c) conditional flag
d) all of the mentioned

View Answer

Answer: a [Reason:] The register set of 80486 is similar to that of the 80386 but only a flag called as alignment check flag is added to the flag register of 80386 to obtain the flag register of 80486.

6. The major limitation of 80386-387 system is
a) low speed
b) 80386 sends data using an I/O handshake technique
c) 80386 returns to real mode by reset operation
d) none of the mentioned

View Answer

Answer: b [Reason:] The major limitation of 80386-387 system is that the 80386 sends instruction or data to 80387 using an I/O handshake technique. To perform this handshaking and to carry additional house keeping tasks, 80386 requires 15 clock cycles or more.

7. The datatype that the 80486 doesnot support is
a) Signed and unsigned
b) ASCII
c) Floating point
d) None

View Answer

Answer: d [Reason:] The datatypes that 80486 supports are 1. Signed 2. Unsigned 3. Floating point 4. BCD 5. String 6. ASCII.

8. In Little Endian data format, the data is stored as
a) MSB is stored at lower memory address and LSB at higher memory address
b) LSB is stored at lower memory address and MSB at higher memory address
c) MSB is stored at general purpose registers
d) LSB is stored at general purpose registers

View Answer

Answer: b [Reason:] In Little Endian data format, for a data of size bigger than 1 byte, the LSB is stored at lower memory address and MSB at higher memory address.

9. The on-chip cache is used for storing
a) addresses of data
b) opcodes and data
c) data and their addresses
d) opcodes and their addresses

View Answer

Answer: b [Reason:] The unique feature of 80486 that is not available in 80386 is that the on-chip is used for storing opcodes and data.

10. The on-chip cache is controlled by
a) Cache disable(CD)
b) No write through(NW)
c) Cache disable and No write through
d) None of the mentioned

View Answer

Answer: c [Reason:] Cache disable(CD) and No write through(NW) bits of control register CR0. To completely disable cache, the CD and NW bits must be 11.

11. The on-chip cache can be flushed using external hardware using
a) FLUSH pin
b) TERMINATE pin
c) FLOW pin
d) Pin FLUSH# or using software

View Answer

Answer: d [Reason:] The on-chip cache can be flushed using external hardware using pin FLUSH# or using software. The flushing operation clears all the valid bits for all the cache lines.