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Interview MCQ Set 1

1. The external interrupts of 8051 can be enabled by
a) 4 LSBs of TCON register
b) Interrupt enable
c) priority register
d) all of the mentioned

View Answer

Answer: d [Reason:] The external interrupts namely INT0(active low) and INT1(active low) can be enabled and programmed using the least significant four bits of TCON register and the Interrupt enable and priority registers.

2. The bits that control the external interrupts are
a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2

View Answer

Answer: c [Reason:] The bits, EX0 and EX1 individually control the external interrupts, INT0(active low) and INT1(active low). If INT0(active low) and INT1(active low) interrupts are to be enabled then the bits EX0 and EX1 must be set respectively.

3. EA bit is used to
a) enable or disable external interrupts
b) enable or disable internal interrupts
c) enable or disable all the interrupts
d) none of the mentioned

View Answer

Answer: c [Reason:] Using EA bit, all the interrupts can be enabled or disabled. Using the individual respective bit, the respective interrupt can be enabled or disabled.

4. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: b [Reason:] Each interrupt level of 8051 can have two levels of priority namely level 0 and level 1. Level 1 is considered as a higher priority level compared to level 0.

5. The priority level of interrupt of 8051 for which SI(serial interrupt) interrupt is programmed is
a) level 0
b) level 1
c) level 0 or level 1
d) none

View Answer

Answer: b [Reason:] SI interrupt is programmed for level 1 priority.

6. The interrupt bit that when set works at level 1, and otherwise at level 0 is
a) PT1
b) PT0
c) PX1
d) All of the mentioned

View Answer

Answer: d [Reason:] The bits, PT1, PT0, PX0 and PX1 when set, work at level 1, otherwise at level 0.

7. All the interrupts at level 1 are polled in the second clock cycle of the
a) forth T state
b) fifth T state
c) third T state
d) none

View Answer

Answer: b [Reason:] All the interrupts at level 1 are polled or sensed in the second clock cycle of the fifth T state or 9th clock cycle out of 12 clock cycles. Then all the interrupts at level 0 are also polled in the same cycle.

8. The minimum duration of the active low interrupt pulse for being sensed without being lost must be
a) greater than one machine cycle
b) equal to one machine cycle
c) greater than 2 machine cycles
d) equal to 2 machine cycles

View Answer

Answer: b [Reason:] The minimum duration of the active low interrupt pulse should be equal to the duration of one machine cycle for being sensed, else it will be lost.

9. If two interrupts, of higher priority and lower priority occur simultaneously, then the service provided is for
a) interrupt of lower priority
b) interrupt of higher priority
c) lower & higher priority interrupts
d) none of the mentioned

View Answer

Answer: b [Reason:] If two interrupts, occur simultaneously, then the one with higher priority level and early polling sequence will receive service. The other one with lower priority may get lost there, as there is no mechanism for storing the interrupt requests.

10. For an interrupt to be guaranteedly served it should have duration of
a) one machine cycle
b) three machine cycles
c) two machine cycles
d) four machine cycles

View Answer

Answer: c [Reason:] For an interrupt to be guaranteedly served it should have duration of two machine cycles.

11. The service to an interrupt will be delayed if it appears during the execution of
a) RETI instruction
b) Instruction that writes to IE register
c) Instruction that writes to IP register
d) All of the mentioned

View Answer

Answer: d [Reason:] The service to an interrupt will be delayed if it appears during the execution of RETI instruction or the instruction that writes to IE/IP registers.

Interview MCQ Set 2

1. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program

View Answer

Answer: c [Reason:] An interrupt function is to break the sequence of operation.

2. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit

View Answer

Answer: a [Reason:] An interrupt transfers the control to interrupt service routine (ISR). After executing ISR, the control is transferred back again to main program.

3. While executing main program, if two or more interrupts occur, then the sequence of appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt

View Answer

Answer: d [Reason:] If an interrupt occurs while executing a program, and the processor is executing the interrupt, if one more interrupt occurs again, then it is called nested interrupt.

4. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability

View Answer

Answer: c [Reason:] The processor if handles more devices as interrupts then it has multiple interrupt processing ability.

5. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned

View Answer

Answer: a [Reason:] NMI is the acronym for nonmaskable interrupt.

7. If any interrupt request given to an input pin cannot be disabled by any means then the input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned

View Answer

Answer: b [Reason:] A nonmaskable interrupt input pin is one which means that any interrupt request at NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.

8. The INTR interrupt may be
a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned

View Answer

Answer: a [Reason:] the INTR (interrupt request) is maskable or can be disabled.

9. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request

View Answer

Answer: b [Reason:] If more than one interrupt request (INTR) occurs at a time, then an external chip called programmmable interrupt controller is required to handle them.

10. The INTR interrupt may be masked using the flag
a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag

View Answer

Answer: c [Reason:] If microprocessor wants to serve any interrupt then interrupt flag, IF=1. If interrupt flag, IF=0, then the processor ignores the service.

Interview MCQ Set 3

1. The 8089 shares the system bus and memory with the host CPU in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned

View Answer

Answer: a [Reason:] In a tightly coupled configuration, the 8089 shares the system bus and memory with the host CPU using its RQ (active low) or GT (active low) pins.

2. The 8089 communicates with the host CPU using bus arbiter and controller in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned

View Answer

Answer: b [Reason:] In a loosely coupled configuration, the 8089 has its own local bus and communicates with the host CPU using bus arbiter and controller.

3. The number of address lines used by the I/O processor in 8089 is
a) 20
b) 12
c) 16
d) 8

View Answer

Answer: c [Reason:] The 8089 I/O processor uses only 16 address lines, and thus it can address only 64KB of IO space.

4. The IO device that can be interfaced with 8089 is
a) 16-bit IO
b) 8-bit IO
c) 64-bit IO
d) 16-bit and 8-bit IO

View Answer

Answer: d [Reason:] The 8089 handled IO devices need not have the same data bus width as that of 8089. This enables even 8-bit IO devices to be interfaced easily with 8089.

5. In the 8089 architecture, the address of memory table for channel-2 is calculated by
a) adding 16 to the contents of CCP
b) adding 8 to the contents of CCP
c) adding memory table address of channel-1
d) none of the mentioned

View Answer

Answer: b [Reason:] The address of the memory table for channel-2 is calculated by adding 8 to the contents of CCP or by adding memory table address for channel-1 to the contents of CCP.

6. Which of the following is not a general purpose register of 8089?
a) GA
b) BC
c) CX
d) MC

View Answer

Answer: c [Reason:] The registers GA, GB, GC, BC, IX and MC can be used as general purpose registers.

7. The registers that are used as source and destination pointers during DMA operations are
a) GB, GC
b) GC, BC
c) GC, GA
d) GA, GB

View Answer

Answer: d [Reason:] GA register is used as source and GB as destination pointers during DMA operations.

8. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ (active low) or GT (active low)

View Answer

Answer: c [Reason:] The DRQ and EXT are used for data transfer control and operation termination signals during DMA operations.

9. The pin that is used to inform the CPU that the previous operation is completed is
a) RQ (active low)
b) GT (active low)
c) DRQ
d) SINTR

View Answer

Answer: d [Reason:] The SINTR pins are used by the channels either to inform the CPU that the previous operation is over or to ask for its attention or interference if required, before the completion of the task.

10. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned

View Answer

Answer: d [Reason:] The program status word contains the current channel status, which contains source and destination address widths, channel activity, interrupt control and servicing, bus load limit and priority information.

Interview MCQ Set 4

1. The registers that store the keyboard and display modes and operations programmed by CPU are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers

View Answer

Answer: b [Reason:] The control and timing registers store the keyboard and display modes and other operations programmed by CPU.

2. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode

View Answer

Answer: c [Reason:] In this mode, each key code of the pressed key is entered in the order of the entry, and in the meantime, read by the CPU, till the RAM becomes empty.

3. The registers that holds the address of the word currently being written by the CPU from the display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers

View Answer

Answer: d [Reason:] The display address registers holds the address of the word currently being written or read by the CPU to or from the display RAM.

4. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode

View Answer

Answer: c [Reason:] In scanned keyboard mode with 2 key lockout mode of operation, when a key is pressed, a debounce logic comes into operation. During the next two scans, other keys are checked for closure and if no other key is pressed then the first pressed key is identified.

5. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode

View Answer

Answer: a [Reason:] The scanned keyboard special error mode is programmed using end interrupt/error mode set command. This mode is valid only under the N-key rollover mode.

6. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode

View Answer

Answer: b [Reason:] In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM.

7. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none

View Answer

Answer: a [Reason:] The data that is entered from the left side of the display unit is of left entry mode, as in a type-writer the first character typed appears at the left-most position, while the subsequent characters appear successively to the right of the first one.

8. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode

View Answer

Answer: c [Reason:] Overrun error occurs, when an already full FIFO is attempted an entry. Underrun error occurs when an empty FIFO read is attempted.

9. The flag that increments automatically after each read or write operation to the display RAM is
a) IF
b) RF
c) AI
d) WF

View Answer

Answer: c [Reason:] AI refers to auto increment flag.

10. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ line
a) goes low
b) goes high
c) remains unchanged
d) none

View Answer

Answer: b [Reason:] In sensor matrix mode, the IRQ line goes high, if any change in sensor value is detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU.

Interview MCQ Set 5

1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned

View Answer

Answer: c [Reason:] Machine language instruction format has one or more fields. The first one is the operation code field.

2. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned

View Answer

Answer: c [Reason:] Machine language instruction format has both the fields.

3. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes

View Answer

Answer: b [Reason:] This format is only one byte long.

4. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes

View Answer

Answer: a [Reason:] This format is 2 byte long.

5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operand
d) all of the mentioned

View Answer

Answer: d [Reason:] The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other operand.

6. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned

View Answer

Answer: c [Reason:] The S-bit known as sign extension bit is used along with W-bit to show the type of operation.

7. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit

View Answer

Answer: d [Reason:] The Z-bit is used by the REP instruction to control the loop.

8. If W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits

View Answer

Answer: c [Reason:] If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-bits.

9. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned

View Answer

Answer: a [Reason:] The sequential control flow instructions follow sequence order in their execution.

10. The instructions that transfer the control to some predefined address or the address specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned

View Answer

Answer: b [Reason:] The control transfer instructions transfer control to the specified address.

11. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions

View Answer

Answer: d [Reason:] The JUMP instruction transfers the control to the address located in the instruction.