Generic selectors
Exact matches only
Search in title
Search in content
Search in posts
Search in pages
Filter by Categories
nmims post
Objective Type Set
Online MCQ Assignment
Question Solution
Solved Question
Uncategorized

Interview MCQ Set 1

1. The 8257 is able to accomplish the operation of
a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned

View Answer

Answer: d [Reason:] The 8257 can accomplish three types of operations and they are i) verify DMA operation ii) write operation iii) read operation.

2. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned

View Answer

Answer: b [Reason:] If the HLDA signal is received by the DMA controller, it indicates that the bus is available.

3. To indicate the I/O device that its request for the DMA transfer has been honoured by the CPU, the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK (active low)
d) DACK (active high)

View Answer

Answer: c [Reason:] The DACK (active low) line of the used channel is pulled down by the DMA controller to indicate the I/O device that its request for the DMA transfer has been honoured by the CPU.

4. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned

View Answer

Answer: c [Reason:] If more than one channel requests service simultaneously, then the transfer occurs as a burst or continuous transfer.

5. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK (active low)
c) DACK (active high)
d) HLDA

View Answer

Answer: d [Reason:] The burst or continuous transfer may be interrupted by an external device by pulling down the HLDA line.

6. The number of clock cycles required for a 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned

View Answer

Answer: b [Reason:] The 8257 uses four clock cycles to complete a transfer.

7. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to be in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned

View Answer

Answer: b [Reason:] In this scheme, the DRQ3 has the lowest priority followed by DRQ2 and DRQ1. The DRQ0 has the highest priority.

8. The priority of the channels varies frequently in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned

View Answer

Answer: a [Reason:] In this scheme, the priorities assigned to the channels are not fixed.

9. The register of 8257 that can only be written in is
a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register

View Answer

Answer: c [Reason:] The selected register may be read or written depending on the instruction executed by the CPU. But only write operation can be performed on the mode set register.

10. The operation that can be performed on the status register is
a) write operation
b) read operation
c) read and write operations
d) none of the mentioned

View Answer

Answer: b [Reason:] The status register can only be read.

Interview MCQ Set 2

1. The advantage of dynamic RAM is
a) high packing density
b) low cost
c) less power consumption
d) all of the mentioned

View Answer

Answer: d [Reason:] The dynamic RAM is advantageous than the static RAM as it has higher packing density, lower cost and less power consumption.

2. Whenever a large memory is required in a microcomputer system, the memory subsystem is generally designed using
a) Static RAM
b) Dynamic RAM
c) Both static and dynamic RAM
d) ROM

View Answer

Answer: b [Reason:] Dynamic RAM is preferred for large memory.

3. If a typical static RAM cell require 6 transistors then corresponding dynamic RAM requires
a) 1 transistor along with capacitance
b) 2 transistors along with resistance
c) 3 transistors along with diode
d) 2 transistors along with capacitance

View Answer

Answer: a [Reason:] The hardware complexity of dynamic RAM is lesser than that of static RAM.

4. To store the charge as a representation of data, the basic dynamic RAM cell uses
a) resistor
b) capacitor
c) diode
d) transistor

View Answer

Answer: c [Reason:] The basic dynamic RAM cell uses capacitance to store the charge as a representation of data. This capacitor is manufactured as a diode that is reverse biased so that the storage capacitance is obtained.

5. The process of refreshing the data in the RAM to reduce the possibility of data loss is known as
a) data cycle
b) regain cycle
c) retain cycle
d) refresh cycle

View Answer

Answer: d [Reason:] The data storage in RAM which is capacitance (reverse-biased diode) may have a leakage current that tends to discharge the capacitor giving rise to possibility of data loss. To avoid this, the data must be refreshed after a fixed time interval regularly.

6. The field in which dynamic RAM is more complicated than static RAM is
a) complexity
b) interfacing circuit
c) execution unit
d) cost

View Answer

Answer: b [Reason:] The refresh mechanism and the additional hardware required makes the interfacing circuit of dynamic RAM more complicated than that of static RAM.

7. Memory refresh activity is
a) initialised by processor
b) initialised by external bus master
c) initialised by refresh mechanism
d) initialised either by processor or by external bus

View Answer

Answer: c [Reason:] The refresh operation is independent regular activity that is initialised and carried out by the refresh mechanism.

8. The number of memory chips that are enabled at a time for refresh activity is
a) 2
b) 4
c) 8
d) more than 1

View Answer

Answer: d [Reason:] More than one memory chip can be enabled at a time for refresh activity to reduce the number of total memory refresh cycles.

9. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is
a) constant timer
b) data managing timer
c) refresh timer
d) qualitative timer

View Answer

Answer: c [Reason:] Refresh timer derives a pulse for refreshing action after each refresh interval which can be qualitatively defined as the time for which a dynamic RAM cell can hold data charge level practically constant.

10. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as
a) n*td
b) td/n
c) n/td
d) tdn

View Answer

Answer: b [Reason:] Refresh time is the ratio of time duration taken for refreshing to the number of rows that are refreshed. Refresh frequency is the reciprocal of refresh time.

Interview MCQ Set 3

1. Which of the following is not a newly added instruction of 80386, that are not present in 80286?
a) bit scan instructions
b) bit test instructions
c) shift double instructions
d) none of the mentioned

View Answer

Answer: d [Reason:] The newly added instructions of 80386 are categorized into 1. bit scan instructions 2. bit test instructions 3. conditional set byte instructions 4. shift double instructions 5. control transfer via gates instructions.

2. The BSF (bit scan forward) instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned

View Answer

Answer: b [Reason:] The BSF (bit scan forward) instruction scans the operand from right to left.

3. The BSR (bit scan reverse) instruction scans the operand in the order
a) from left to right
b) from right to left
c) from upper nibble
d) none of the mentioned

View Answer

Answer: a [Reason:] The BSR (bit scan reverse) instruction scans the operand from left to right.

4. If a ‘1’ is encountered when operand is scanned by BSF, then
a) zero flag is reset
b) zero flag is set
c) VM flag is set
d) RF flag is reset

View Answer

Answer: b [Reason:] The BSF instruction scans the operand from right to left. If a ‘1’ is encountered during the scan, zero flag is set, and the bit position of ‘1’ is stored into the destination operand.

5. If a ‘1’ is not encountered when operand is scanned by BSR, then
a) zero flag is reset
b) zero flag is set
c) VM flag is reset
d) RF flag is set

View Answer

Answer: a [Reason:] The BSR instruction scans the operand from left to right. If a ‘1’ is not encountered during the scan, zero flag is reset whether the scan is BSF or BSR.

6. Which of the following is not a bit test instruction?
a) BTC
b) BTS
c) BSF
d) BTR

View Answer

Answer: c [Reason:] The instruction, BSF, is a bit scan instruction. The four bit test instructions are: BT (Test a Bit), BTC (Test a Bit and Complement), BTR (Test and Reset a Bit) and BTS (Test and Set a bit).

7. In case of BT instruction, if the bit position in the destination operand specified by the source operand, is ‘1’, then
a) zero flag is reset
b) carry flag is set
c) VM flag is set
d) RF flag is reset

View Answer

Answer: b [Reason:] In case of BT instruction, if the bit position in the destination operand specified by the source operand, is ‘1’, the carry flag is set, otherwise it is cleared.

8. Which of the following is not a conditional set byte instruction?
a) SETNP
b) SETO
c) SETNAE
d) SHRD

View Answer

Answer: d [Reason:] The SHRD (Shift Right Double) is a shift double instruction.

9. The instruction that shifts the specified number of bits in the instruction, from the upper side of the source operand into the lower side of the destination operand is
a) SHRD
b) SHLD
c) SETNS
d) None of the mentioned

View Answer

Answer: b [Reason:] The SHLD instruction shifts the specified number of bits in the instruction, from the upper side (i.e. MSB) of the source operand into the lower side (i.e. LSB) of the destination operand.

10. The instruction that shifts 8 LSB bits of ECX into the MSB positions of EAX, one by one starting from LSB of ECX is
a) SHLD ECX,EAX,8
b) SHLD EAX,ECX,8
c) SHRD ECX,EAX,8
d) SHRD EAX,ECX,8

View Answer

Answer: d [Reason:] The SHRD instruction shifts the specified number of bits in the instruction, from lower side (i.e. LSB) of the source operand into the the upper side (i.e. MSB) of the destination operand.

Interview MCQ Set 4

1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned

View Answer

Answer: d [Reason:] Pentium 4 is based on NetBurst microarchitecture. Clock speed varies from 1.4GHz to 1.7GHz. It has hyper-pipelined technology.

2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none

View Answer

Answer: c [Reason:] Pentium 4 architecture may be viewed having four basic modules. 1. Front end module 2. Out of order execution engine 3. Execution module 4. Memory subsystem module.

3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned

View Answer

Answer: d [Reason:] The front module of Pentium 4 contains 1. IA 32 Instruction decoder 2. Trace cache 3. Microcode ROM 4. Front end branch predictor.

4. The unit that decodes the instructions concurrently and translate them into micro-operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor

View Answer

Answer: b [Reason:] The role of instruction decoder is to decode the instructions concurrently and translate them into micro-operations known as micro-ops.

5. In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none

View Answer

Answer: c [Reason:] In case of complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to microcode ROM.

6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none

View Answer

Answer: a [Reason:] The trace cache is a special instruction cache because it does not store the instructions, but the decoded stream of instructions.

7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops

View Answer

Answer: d [Reason:] Trace cache can store upto 12K micro-ops. The cache assembles the decoded micro-ops into ordered sequence of micro-ops called traces.

8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder

View Answer

Answer: b [Reason:] The front end branch predictor predicts the locations from where the next instruction bytes are fetched.

9. If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder

View Answer

Answer: a [Reason:] When some complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to microcode ROM.

10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder

View Answer

Answer: a [Reason:] After the micro-ops are issued by the microcode ROM, the control goes to Trace cache once again. The micro-ops delivered by the trace cache and the microcode ROM are buffered in a queue in an orderly fashion.

Interview MCQ Set 5

1. The basic principle of floppy disks involve
a) magnetic data reading
b) magnetic data recording
c) magnetic data recording and reading
d) none of the mentioned

View Answer

Answer: c [Reason:] Whatever their physical sizes and storage formats, all the floppies incorporate the basic principles of magnetic data recording and reading.

2. In floppy disk, the small hole that enables the drive to identify the beginning of a track and its first sector is
a) inner hole
b) key hole
c) index hole
d) start hole

View Answer

Answer: c [Reason:] The small hole called index hole, enables the drive to identify the beginning of a track and its first sector.

3. Inside its jacket, the floppy media is rotated at the speed of
a) 200 RPM
b) 300 RPM
c) 150 RPM
d) 50 RPM

View Answer

Answer: b [Reason:] The floppy media is rotated at the speed of 300 RPM (Revolution Per Minute) inside its jacket.

4. The Double Density Double Sided disks on each side are organised with
a) 20 tracks
b) 30 tracks
c) 40 tracks
d) 50 tracks

View Answer

Answer: c [Reason:] The Double Density Double Sided (DDDS) disks are organised with 40 tracks on each side of the disk.

5. The magnetic recording technique used for storing data onto the disks (floppy disks) is called
a) return to zero
b) non-return to zero
c) return to zero and Non-return to zero
d) none of the mentioned

View Answer

Answer: b [Reason:] In this technique, the magnetic flux on the disk surface never returns to zero, i.e. no erase operation is carried out.

6. For reading the disks DVD uses
a) blue laser
b) white laser
c) red laser
d) green laser

View Answer

Answer: c [Reason:] A DVD is an optical disk that uses a red laser for reading the disks.

7. For reading the disks, the blue ray disk uses
a) high frequency red laser
b) low frequency red laser
c) high frequency blue laser
d) low frequency blue laser

View Answer

Answer: c [Reason:] The blue ray disk uses a high frequency blue laser with a small wavelength to read the disk.

8. A blue ray disk can store data upto _________ per layer.
a) 25 KB
b) 25 MB
c) 25 TB
d) 25 GB

View Answer

Answer: d [Reason:] A blue ray disk can store data upto 25 GB per layer and is popularly used for storing long duration videos like movies.

9. DVDRW is for
a) read-write DVD
b) rewriteable DVD
c) recordable DVD
d) none of the mentioned

View Answer

Answer: b [Reason:] DVDRW is for rewriteable DVD and DVDR is for recordable DVD.

10. The HDD is also called as
a) hard disk
b) hard drive
c) fixed disk
d) all of the mentioned

View Answer

Answer: d [Reason:] The Hard Disk Drive is also called as hard disk, hard drive, fixed drive, fixed disk or fixed disk drive.