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Interview MCQ Set 1

1. Which of the units is not a part of internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned

View Answer

Answer: d [Reason:] The internal architecture of 80386 is divided into three sections namely, central processing unit, memory management unit and bus interface unit.

2. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit

View Answer

Answer: c [Reason:] The central processing unit is further divided into execution unit and instruction unit.

3. The unit that is used for handling data, and calculate offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit

View Answer

Answer: b [Reason:] The execution unit has eight general purpose and eight special purpose registers, which are either used for handling the data or calculating the offset addresses.

4. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter

View Answer

Answer: c [Reason:] The instruction unit decodes the opcode bytes, received from the 16-byte instruction code queue, after decoding them so as to pass it to the control section, for deriving the necessary control signals.

5. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter

View Answer

Answer: d [Reason:] The barrel shifter speeds up all shift and rotate operations.

6. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned

View Answer

Answer: c [Reason:] The memory management unit consists of a segmentation unit and a paging unit.

7. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned

View Answer

Answer: d [Reason:] The segmentation unit allows the use of two address components. They are: segment and offset for relocation and sharing of code and data.

8. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit

View Answer

Answer: c [Reason:] The paging unit organizes the physical memory, in terms of pages of 4KB size each.

9. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit

View Answer

Answer: b [Reason:] The paging unit works under the control of segmentation unit; i.e. each segment is further divided into pages.

10. The unit that provides a four level protection mechanism, for system’s code and data against application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned

View Answer

Answer: b [Reason:] The segmentation unit provides a four level protection mechanism, for protecting and isolating the system’s code and data, from those of the application program.

11. The unit that has a prioritizer to resolve the priority of the various bus requests is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit

View Answer

Answer: c [Reason:] The bus control unit has a prioritizer to resolve the priority of the various bus requests.

12. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit

View Answer

Answer: b [Reason:] The data buffer interfaces the internal data bus with the system bus.

13. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver

View Answer

Answer: c [Reason:] The address driver drives the bus enable and address signals A0-A31.

14. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) None of the mentioned

View Answer

Answer: b [Reason:] The Next Address (NA) input pin, if activated, allows address pipelining, during 80386 bus cycles.

15. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ

View Answer

Answer: c [Reason:] READY signal is used to insert WAIT states in a bus cycle, and is useful for interfacing of slow devices with the CPU.

16. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ

View Answer

Answer: d [Reason:] The Processor Extension Request (PEREQ) output signal indicates to the CPU to fetch a data word for the coprocessor.

17. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned

View Answer

Answer: c [Reason:] The pipeline and dynamic bus sizing units handle the related control signals.

Interview MCQ Set 2

1. The assembler directives which are the hints using some predefined alphabetical strings are given to
a) processor
b) memory
c) assembler
d) processor & assembler

View Answer

Answer: c [Reason:] These directives help the assembler to correctly understand the assembly language programs to prepare the codes.

2. The directive used to inform the assembler, the names of the logicals segments to be assumed for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB

View Answer

Answer: a [Reason:] In ALP, each segment is given a name by using the directive ASSUME SYNTAX: ASSUME segment:segment_name Eg: ASSUME CS:Code here CS is the Code segment and code is the name assumed to the segment.

3. Match the following

   a) DB          1) used to direct the assembler to reserve only 10-bytes
   b) DT          2) used to direct the assembler to reserve only 4 words
   c) DW          3) used to direct the assembler to reserve byte or bytes
   d) DQ          4) used to direct the assembler to reserve words

a) a-3, b-2, c-4, d-1
b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2

View Answer

Answer: d [Reason:] These directives are used for allocating memory locations in the available memory.

4. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned

View Answer

Answer: b [Reason:] The directive END is used to denote the completion of the program.

5. The directive that marks the end of a logical segment is
a) ENDS
b) END
c) ENDS & END
d) None of the mentioned

View Answer

Answer: a [Reason:] The directive ENDS is used to end a segment where as the directive END is used to end the program.

6. The directive that updates the location counter to the next even address while executing a series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU

View Answer

Answer: b [Reason:] The directive updates location counter to next even address if the current location counter contents are not even.

7. The directive that directs the assembler to start the memory allotment for a particular segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP

View Answer

Answer: c [Reason:] If an ORG is written then the assembler initiates the location counter to keep the track of allotted address for the module as mentioned in the directive. If the directive is not present, then the location counter is initialised to 0000H.

8. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC

View Answer

Answer: b [Reason:] The directive SEGMENT indicates the beginning of the segment.

9. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU

View Answer

Answer: d [Reason:] In this, the recurring/repeating value is assigned with a label.The label is placed instead of the numerical value in the entire program code.

10. The labels or constants that can be used by any module in the program is possible when they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL

View Answer

Answer: c [Reason:] The labels, constants, variables, procedures declared as GLOBAL can be used by any module in the program.

Interview MCQ Set 3

1. Which of the following is an incorporated function to resolve interprocessor communication problems?
a) bus allotment and control
b) bus arbitration
c) priority resolving
d) all of the mentioned

View Answer

Answer: d [Reason:] To resolve the various bus contention and interprocessor communication problems, different hardware strategies and algorithms are worked out. These incorporated functions like bus allotment and control, bus arbitration and priority resolving into them.

2. The device that deals with the bus access control functions and bus handshake activities is
a) bus allotment controller
b) bus arbiter
c) priority resolver
d) none of the mentioned

View Answer

Answer: b [Reason:] The bus arbiter or 8289 takes care of bus access control functions and bus handshake activities.

3. The clock generator delays the READY signal until the signal _________ goes low
a) DEN (active high)
b) DEN (active low)
c) AEN (active low)
d) AEN (active high)

View Answer

Answer: c [Reason:] If AEN (active low) is high, the clock generator delays the READY signal till the AEN (active low) goes low.

4. The bus controller relinquishes the bus if
a) READY (active low)
b) LOCK (active high)
c) CBRQ (active low)
d) BPRO (active high)

View Answer

Answer: b [Reason:] The bus controller does not relinquish (release its control on) the bus, till the LOCK (active low) input is low.

5. The signals that are used by the bus arbitration in the independent request method is
a) BREQ (active low)
b) BPRN (active low)
c) CBRQ (active low)
d) All of the mentioned

View Answer

Answer: d [Reason:] The four active low signals, bus request (BREQ), bus priority in (BPRN), common bus request (CBRQ) and bus priority out (BPRO) are used for bus arbitration.

6. The signal that is used to drive a priority resolving network that actually accepts the bus request inputs is
a) BREQ (active low)
b) BPRN (active low)
c) CBRQ (active low)
d) BPRO (active low)

View Answer

Answer: a [Reason:] The BREQ (active low) is used to drive a priority resolving network that actually accepts the bus request inputs from all the masters and derives the priority outputs which further drive the BPRN (active low) inputs of all the masters.

7. Which of the following is the simplest and cheapest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned

View Answer

Answer: a [Reason:] The daisy chaining method is the simplest one, as it has less hardware complexity.

8. The method of bus arbitration that does not contain priority resolving network in it is
a) daisy chaining
b) independent request
c) polling
d) none

View Answer

Answer: a [Reason:] The daisy chaining method does not contain any priority resolving network, rather the priorities of all the devices are essentially assumed to be in sequence.

9. Which of the following is the fastest method of bus arbitration?
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned

View Answer

Answer: b [Reason:] The independent request scheme is quite fast, because each of the masters can independently communicate with the controller.

10. A set of address lines is driven by the controller in
a) daisy chaining
b) independent request
c) polling
d) none of the mentioned

View Answer

Answer: c [Reason:] In polling scheme, a set of address lines is driven by the controller to address each of the masters in sequence.

Interview MCQ Set 4

1. The files that reside in the current drive and directory of the hard disk is
a) OBJ files
b) EXE files
c) SRC files
d) DEST files

View Answer

Answer: b [Reason:] The files that reside in the current drive and directory of the hard disk is EXE files.

2. The master processor stores the result buffers on to the hard disk with the filename as
a) .EXE file
b) .OBJ file
c) .EXE file with extension .RES
d) .OBJ file with extension .RES

View Answer

Answer: c [Reason:] The master processor stores the result buffers on to the hard disk with the filename as .EXE file with extension .RES.

3. The 8288 bus controller chip derives the signals
a) ALE
b) DEN
c) DT/R(active low)
d) All of the mentioned

View Answer

Answer: d [Reason:] The latches are enabled by ALE signal and data will be enabled by DEN signal. The ALE, DEN and DT/R(active low) signals are derived by a seperate 8288 bus controller chip.

4. The EXE files should not exceed the size of
a) 30 KB
b) 50 KB
c) 60 KB
d) 40 KB

View Answer

Answer: c [Reason:] The EXE files should not be more than 60 KB size.

5. A part of memory that can be addressed by more than one processor for communication is known as
a) memory module
b) bus window
c) ram
d) memory management unit

View Answer

Answer: b [Reason:] There are two slave processors and thus there are two bus windows.

6. When a subprocessor wants to communicate with the bus window, it informs the main processor to
a) enable control buffer
b) storage buffer
c) disable tristate buffer
d) translation look aside buffer

View Answer

Answer: c [Reason:] An 8255 IO card is used to control the tristate buffers that provide isolation. When a subprocessor wants to communicate with the bus window, it informs the main processor to disable tristate buffer.

7. When the subprocessor completes its execution, then the status on the status lines shows
a) hold status
b) halt status
c) high status
d) low status

View Answer

Answer: b [Reason:] When the subprocessor completes its execution, then the status on the status lines shows halt status.

8. For MEMR(active low) and MEMWR(active low) operations the mode of isolation buffer should respectively be in
a) receiver mode, receiver mode
b) transmit mode, receiver mode
c) receiver mode, transmit mode
d) transmit mode, transmit mode

View Answer

Answer: c [Reason:] During MEMR(active low) the data flows from memory to CPU so isolation buffer should be in receiver mode and data flows from CPU to memory during MEMWR(active low) operation and so buffer should be in transmit mode.

9. If the DIR pin of the isolation chip is high, then it enters into
a) receiver mode
b) virtual access mode
c) transmit or receive mode
d) transmit mode

View Answer

Answer: d [Reason:] If the DIR pin of the isolation chip is high, then it enters into transmit mode and if it is 0 then isolation chip enters into receiver mode.

10. The complete software system is divided into
a) main program
b) Interrupt routine IRT2 for first subprocessing the unit
c) Interrupt routine IRT3 for first subprocessing the unit
d) all of the mentioned

View Answer

Answer: d [Reason:] System software of the complete system consists of three parts. the first part main control program controls the total operation of the system, and remaining two parts are the small local initialization programs for each of the subprocessors.

Interview MCQ Set 5

1. In direct memory access mode, the data transfer takes place
a) directly
b) indirectly
c) directly and indirectly
d) none of the mentioned

View Answer

Answer: a [Reason:] In direct memory access mode, the data may transfer directly without the interference from the CPU.

2. In 8257 (DMA), each of the four channels has
a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register

View Answer

Answer: b [Reason:] The DMA supports four channels, and each of the channel has a pair of two 16-bit registers, namely DMA address register and terminal count register.

3. The common register(s) for all the four channels of 8257 are
a) DMA address register
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned

View Answer

Answer: c [Reason:] The two common registers for all the four channels of DMA are mode set register and status register.

4. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when
a) Auto load is set
b) Auto load is reset
c) TC STOP bit is reset
d) TC STOP bit is set

View Answer

Answer: d [Reason:] If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel.

5. The IOR (active low) input line acts as output in
a) slave mode
b) master mode
c) master and slave mode
d) none of the mentioned

View Answer

Answer: b [Reason:] The IOR (active low) is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as output in the master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle.

6. The IOW (active low) in its slave mode loads the contents of data bus to
a) 8-bit mode register
b) upper/lower byte of 16-bit DMA address register
c) terminal count register
d) all of the mentioned

View Answer

Answer: d [Reason:] In its slave mode, the IOW (active low) loads the contents of data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address register or terminal count register.

7. The pin that disables all the DMA channels by clearing the mode registers is
a) MARK
b) CLEAR
c) RESET
d) READY

View Answer

Answer: c [Reason:] The RESET pin which is asynchronous input disables all the DMA channels by clearing the mode registers, and tristates all the control lines.

8. The pin that requests the access of the system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned

View Answer

Answer: b [Reason:] The hold request output requests the access of the system bus.

9. The pin that is used to write data to the addressed memory location, during DMA write operation is
a) MEMR (active low)
b) AEN
c) MEMW (active low)
d) IOW (active low)

View Answer

Answer: c [Reason:] The MEMW (active low) is used to write data to the addressed memory location, during DMA write operation.

10. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is
a) AEN
b) ADSTB
c) TC
d) None of the mentioned

View Answer

Answer: b [Reason:] The pin ADSTB strobes the higher byte of the memory address, generated by the DMA controller into the latches.