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# Multiple choice question for engineering

## Set 1

1. Transistor–transistor logic (TTL) is a class of digital circuits built from
a) Transistors only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors

Answer: d [Reason:] Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors.

2. TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by
a) Resistors
b) Transistors
c) Bipolar junction transistors
d) Resistors and transistors respectively

Answer: b [Reason:] TTL is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by registers.

3. TTL was invented in 1961 by
a) Baker clamp
b) James L. Buie
c) Chris Brown
d) None of the Mentioned

Answer: b [Reason:] TTL was invented in 1961 by James L Buie.

4. The full form of TCTL is
a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) None of the Mentioned

Answer: a [Reason:] The full form of TCTL is transistor-coupled transistor logic.

5. The _______ ancestor to the first personal computers.
a) PARAM 1
b) SATYAM 1
c) KENBAK 1
d) None of the Mentioned

Answer: c [Reason:] The KENBAK 1, ancestor to the first personal computers.

6. TTL inputs are the emitters of a
a) Transistor-transistor logic
b) Multiple-emitter transistor
c) Resistor-transistor logic
d) Diode-transistor logic

Answer: b [Reason:] TTL inputs are the emitters of a multiple-emitter transistor.

7. TTL is a
a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing

Answer: a [Reason:] Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a logic 0 level.

8. Standard TTL circuits operate with a __ volt power supply.
a) 2
b) 4
c) 5
d) 3

Answer: c [Reason:] Standard TTL circuits operate with a 5-volt power supply.

9. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
a) Less
b) More
c) Equal
d) None of the Mentioned

Answer: b [Reason:] TTL devices consume substantially more power than equivalent CMOS devices at rest.

10. A TTL gate may operate inadvertently as an
a) Digital amplifier
b) Analog amplifier
c) Inverter
d) Regulator

Answer: b [Reason:] A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly changing input signal that traverses the unspecified region from 0.8V to 2.2V.

11. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
a) TTL
b) ECL
c) RTL
d) DTL

Answer: a [Reason:] The speed of TTL circuits is limited by the tendency of common emitter circuits to go into saturation due to injection of minority carriers into the collector region.

## Set 2

1. The characteristic equation of J-K flip-flop is
a) Q(n+1)=JQ(n)+K’Q(n)
b) Q(n+1)=J’Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) None of the Mentioned

Answer: a [Reason:] The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ(n)+K’Q(n).

2. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as
a) D flip-flop
b) T flip-flop
c) S-R flip-flop
d) None of the Mentioned

Answer: c [Reason:] In J-K flip-flop, if both the inputs are same then it behaves like S-R flip-flop.

3. In J-K flip-flop , the function K=J is used to realize
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) None of the Mentioned

Answer: c [Reason:] T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

4. The only difference between a combinational circuit and a flip-flop is that
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) None of the Mentioned

Answer: c [Reason:] Both flip-flop and latches are memory elements with clock/control inputs.

5. How many stable states a combinational circuits have?
a) 3
b) 4
c) 2
d) 5

Answer: c [Reason:] The two stable states of combinational circuits are 1 and 0.

6. The flip-flop is only activated by
a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) None of the Mentioned

Answer: c [Reason:] Flip flops can be activated with either a positive or negative edge trigger.

7. The S-R latch composed of NAND gates is called an active low circuit because
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) None of the Mentioned

Answer: b [Reason:] Active low indicates that only an input value of 0 sets or resets the circuit.

8. Both the J-K & the T flip-flop are derived from the basic
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop

Answer: b [Reason:] The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived.

9. The flip-flops which has not any invalid states are
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T

Answer: d [Reason:] Unlike the SR latch, these circuits have no invalid states.

10. What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both a & b
d) Level triggered

Answer: b [Reason:] The triangle on the clock input of a J-K flip-flop mean edge triggered.

11. What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

Answer: c [Reason:] The circle on the clock input of a J-K flip-flop mean negative edge triggered.

12. What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

Answer: d [Reason:] The direct line on the clock input of a J-K flip-flop mean level triggered.

13. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered

Answer: d [Reason:] The half circle on the clock input of a J-K flip-flop mean level triggered.

14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave

Answer: d [Reason:] As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the output.

15. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW

Answer: c [Reason:] Edge triggered device will follow the input condition when there is a transition. And positive edge triggered when transition occurs from LOW to HIGH.

## Set 3

1. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
a) Ring shift
b) Clock
c) Johnson
d) Binary

Answer: a [Reason:] Ring shift can be represented as data carried by one FF & deleted by others.

2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________
a) 1101
b) 0111
c) 0001
d) 1110

Answer: b [Reason:] Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits are 011 and remained bit in register is 1. Therefore, 0111 is required solution.

3. To operate correctly, starting a ring shift counter requires:
a) Clearing all the flip-flops
b) Presetting one flip-flop and clearing all others
c) Clearing one flip-flop and presetting all others
d) Presetting all the flip-flops

Answer: b [Reason:] To operate correctly, starting a ring shift counter requires presetting one flip-flop and clearing all others, so that it can shift to the next bit.

4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position for each clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three

Answer: a [Reason:] If register shifts towards left then it shift by a bit to the left and if register shifts right then it shift to the right by one bit.

5. How many clock pulses will be required to completely load serially a 5-bit shift register?
a) 2
b) 3
c) 4
d) 5

Answer: d [Reason:] To load a bit, we require 1 clock pulse for 1 shift register. So, for 5-bit shift register we would require of 5 clock pulses.

6. How is an strobe signal used when serially loading a shift register?
a) To turn the register on and off
b) To control the number of clocks
c) To determine which output Qs are used
d) To determine the FFs that will be used

Answer: b [Reason:] A strobe ( an auxiliary signal used to help synchronize the real data in an electrical bus when the bus components have no common clock) signal is used to control the number of clocks during serially loading a shift register.

7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms

Answer: b [Reason:] From Q0 to Q3 total of 4 bit shifting takes place. Therefore, 4/150kHz = 26.67 microseconds.

8. What are the three output conditions of a three-state buffer?
a) HIGH, LOW, float
b) 1, 0, float
c) Negative, positive, 0
d) None of the Mentioned

Answer: a [Reason:] Three conditions of a three-state buffer are HIGH, LOW & float.

9. The primary purpose of a three-state buffer is usually:
a) To provide isolation between the input device and the data bus
b) To provide the sink or source current required by any device connected to its output without loading down the output device
c) Temporary data storage
d) To control data flow

Answer: a [Reason:] The primary purpose of a three-state buffer is usually to provide isolation between the input device and the data bus.

10. What is the difference between a ring shift counter and a Johnson shift counter?
a) There is no difference
b) A ring is faster
c) The feedback is reversed
d) The Johnson is faster

Answer: c [Reason:] A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Whereas, a Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage.

## Set 4

1. UP-DOWN counter is a combination of
a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter

Answer: d [Reason:] As the name suggests UP-DOWN, it means that it has up-counter and down-counter as well.

2. UP-DOWN counter is also known as
a) Dual counter
b) Multi counter
c) Multimode counter
d) None of the Mentioned

Answer: c [Reason:] UP-DOWN counter is also known as multimode counter because it has capability of counting upward as well as downwards.

3. In an UP-counter, each flip-flop is triggered by
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop

Answer: b [Reason:] In an UP-counter, each flip-flop is triggered by the normal output of the preceding flip-flop.

4. In DOWN-counter, each flip-flop is triggered by
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop

Answer: d [Reason:] In DOWN-counter, each flip-flop is triggered by the inverted output of the preceding flip-flop.

5. Binary counter that count incrementally and decremently is called
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter

Answer: a [Reason:] Binary counter that count incrementally and decremently is called UP-DOWN counter/multimode counter.

6. Once an up-/down-counter begins its count sequence, it
a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) None of the Mentioned

Answer: d [Reason:] In up/down ripple counter once the counting begins, we can simply change the pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.

7. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5

Answer: c [Reason:] In a 4-bit up-down counter, there are 4 J-K flip-flops required.

8. A modulus-10 counter must have ________
a) 10 flip-flops
b) Flip-flops
c) 2 flip-flops
d) Synchronous clocking

Answer: b [Reason:] For any number of modulus we need only 1 flip flop. Because it takes 1 bit but works as a many modulus.

9. Which is not an example of a truncated modulus?
a) 8
b) 9
c) 11
d) 15

Answer: a [Reason:] An n-bit counter whose modulus is less than the maximum possible is called a truncated counter.

10. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH

Answer: a [Reason:] The designation means that the up count is active-HIGH, the down count is active-LOW.

11. An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________
a) Taking the output on the other side of the flip-flops ( instead of Q)
b) Clocking of each succeeding flip-flop from the other side ( instead of Q)
c) Changing the flip-flops to trailing edge triggering
d) All of the Mentioned

Answer: d [Reason:] By all of the mentioned ideas, an asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter.

12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the most significant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz

Answer: a [Reason:] Input clock is given by: 20/2 kHz. So, count on basis of 10 kHz clock. And MSB changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.

## Set 5

1. According to the Nusselt’s film theory, the film thickness decreases as we move from bottom to top. The heat transfer increases.
a) True
b) False

Answer: b [Reason:] According to the Nusselt’s film theory, the film thickness increases as we move from bottom to top. The heat transfer decreases.

2. Statement 1: Unsteady state heat transfer equation can be used when there is negligible internal resistance.
Statement 2: Unsteady state heat transfer equation can be used for liquid food items which are well stirred, because, temperature gradient within won’t be there.
a) True, False
b) True, True
c) False, False
d) False, True

Answer: b [Reason:] Both the statements pertaining to unsteady state heat transfer equation are true.

3. Statement 1: In nusselt’s film theory, velocity of the falling film is not affected by the velocity of the vapors.
Statement 2: LMTD can be used provided the overall heat transfer co-efficient is constant over a large range of temperatures.
a) True, False
b) True, True
c) False, False
d) False, True

Answer: b [Reason:] Both the statements pertaining to Nusselt’s film theory are true.

4. Find heat transfer in an agitated jacketed vessel if NRei is 1.5 * 105 and NPr is 20.
a) 0.9
b) 1.2
c) 1.8
d) None of the mentioned

Answer: a [Reason:] NNu = 0.36 * (NRei) * 0.67 * (NPr) * 0.33 * фv, NNu = hd/k, which is the heat transferred. Substituting values, we get 0.9. фv is neglected.

5. Which of the following is NOT a real dimensionless number?
a) Pectit number
b) Stanton number
c) Graetz number
d) Grashof number

Answer: a [Reason:] Pectit number is NOT a real dimensionless number.

6. Statement 1: NPr= (Cpm)/kl
Statement 2: Stanton number is a product of NRe and NPr.
a) True, False
b) True, True
c) False, False
d) False, True

Answer: c [Reason:] NGz= (Cpm)/kl and NPr= (Cpμ)/k. Pecklet number is a product of NRe and NPr.

7. Statement 1: G is known as the mass flux and it is the product of density and velocity.
Statement 2: Grashof number is associated with forced convection.
a) True, False
b) True, True
c) False, False
d) False, True

Answer: a [Reason:] G is known as the mass flux and it is the product of density and velocity. Grashof number is associated with natural convection.

8. Фv is generally taken as 1 in food processing as generally very high wall temperatures aren’t reached and hence (µ/µw) * 0.14 is 1 as there isn’t much difference in µ and µw.
a) True
b) False

Answer: a [Reason:] фv is generally taken as 1 in food processing as generally very high wall temperatures aren’t reached and hence (µ/µw) * 0.14 is 1 as there isn’t much difference in µ and µw.

9. Statement 1: Sieder-Tate and Dittus-boelter equations imply only to laminar flow conditions.
Statement 2: Under laminar conditions, the same equation applies both to Newtonian and Non-Newtonian fluids.
a) True, False
b) True, True
c) False, False
d) False, True