Multiple choice question for engineering
Set 1
1. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) None of the Mentioned
Answer
Answer: b [Reason:] A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line.
2. Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) None of the Mentioned
Answer
Answer: a [Reason:] Data Selector is another name of Multiplexer.
3. It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of
a) Inputs
b) Outputs
c) Selection lines
d) All of the Mentioned
Answer
Answer: a [Reason:] It is possible for an enable or strobe input to undergo an expansion of two or more MUX ICs to the digital multiplexer with the proficiency of large number of inputs.
4. Which is the major functioning responsibility of the multiplexing combinational circuit?
a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) All of the Mentioned
Answer
Answer: c [Reason:] the major functioning responsibility of the multiplexing combinational circuit is generation of selected path between multiple sources and a single destination because it makes the circuit too flexible.
5. What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Answer
Answer: c [Reason:] Enable input is used to active the chip, when enable is high the chip works (ACTIVE), when enable is low the chip does not work (MEMORY).
6. One multiplexer can take the place of
a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
Answer
Answer: d [Reason:] Since, many operational behaviour can be performed by using a multiplexer. Whereas, a combinational circuit is a combination of many logic gates which makes the circuit more complex.
7. A digital multiplexer is a combinational circuit that selects
a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) None of the Mentioned
Answer
Answer: a [Reason:] A digital multiplexer is a combinational circuit that selects one digital information from several sources and transmits the selected information on a single output line. That is why it is also known as data selector.
8. In a multiplexer, the selection of a particular input line is controlled by
a) Data controller
b) Selected lines
c) Logic gates
d) Both data controller and selected lines
Answer
Answer: b [Reason:] The selection of a particular input line is controlled by a set of selected lines in a multiplexer, which helps to select a particular input from several sources.
9. If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) None of the Mentioned
Answer
Answer: b [Reason:] If the number of n selected input lines is equal to 2^m then it requires m select lines to select one of m select lines.
10. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer
Answer: d [Reason:] 2^n input lines, n control lines and 1 output line available for MUX. Here, 8 input lines mean 2^3 inputs. So, 3 control lines are possible.
11. A basic multiplexer principle can be demonstrated through the use of a
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
Answer
Answer: c [Reason:] A basic multiplexer principle can be demonstrated through the use of a rotary switch. Since, its behaviour is similar to the multiplexer.
12. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
b) 4
c) 2
d) 5
Answer
Answer: c [Reason:] There are two NOT gates required for the construction of 4-to-1 multiplexer. The diagram of a 4-to-1 multiplexer is shown below: 
13. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is
a) X0
b) X1
c) X2
d) X3
Answer
Answer: b [Reason:] The output will be X1, because c1 = 0 is converted into 1 and it is multiplied with c0 = 1 which results as X1. And rest of the AND gates gives output as 0.
14. The enable input is also known as
a) Select input
b) Decoded input
c) Strobe
d) Sink
Answer
Answer: c [Reason:] The enable input is also known as strobe which is used to cascade two or more multiplexer ICs to construct a multiplexer with larger number of inputs.
Set 2
1. Any negative number is recognized by its
a) MSB
b) LSB
c) Bits
d) Nibble
Answer
Answer: a [Reason:] Any negative number is recognized by its MSB.
2. The parameter through which 16 distinct values can be represented is known as:
a) Bit
b) Byte
c) Nibble
d) Word
Answer
Answer: c [Reason:] It can be represented up to 16 different values with the help of Nibble. Though, Nibble is a combination of four bits and it takes four bits to represent a single BCD or hexadecimal digit.
3. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Answer
Answer: b [Reason:] On multiplying the decimal number continuously by 2, the binary equivalent is obtained.
4. The representation of decimal number 532.86 in the form of decimal is
a) 532.65
b) 532.68
c) 531.67
d) 531.68
Answer
Answer: b [Reason:] N= 5 * 102 + 3 * 101 + 2 * 100 + 8 * 10^-1 +6 * 10^-2 = 532.68
5. The binary equivalent of (1011.011)10 is equal to
a) 11.375
b) 10.123
c) 11.175
d) 9.234
Answer
Answer: a [Reason:] 1 * 23 + 0 * 22 + 1 * 21 + 0 * 2^-1 +1 * 2^-2 + 1 * 2^-3 = 11.375
Hence, (1011.011)10 = 11.375
6. An important drawback of binary system is
a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) None of the Mentioned
Answer
Answer: a [Reason:] The most vital drawback of binary system is that it requires very large string of 1’s and 0’s to represent a decimal number.
7. The octal number 645 in power of 8 is equal to
a) 450
b) 451
c) 421
d) 501
Answer
Answer: c [Reason:] The octal number 645 in power of 8 is given by: 6 * 82 + 4 * 81 + 5 * 80 = 421
8. The two digits hexadecimal number which has largest value is ___ which corresponds to _____
a) FE, 255 decimal
b) FF, 254 decimal
c) FF, 255 decimal
d) EF, 245 decimal
Answer
Answer: c [Reason:] The largest of two digit hexadecimal number is FF and corresponds to
15 * 161 + 15 * 160 = 255 (since, F = 15)
9. Representation of hexadecimal number 6DE in the power of 16 is as:
a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Answer
Answer: a [Reason:] In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
10. The quantity of double word is
a) 16 bits
b) 32 bits
c) 64 bits
d) 8 bits
Answer
Answer: b [Reason:] The quantity of double word is 32 bits.
Set 3
1. The given hex number (1E.53)16 is equivalent to
a) (35.68)8
b) (35.24)8
c) (34.34)8
d) (35.59)8
Answer
Answer: b [Reason:] (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100)2
= (011 110.010 100)2
= (35.24)8
2. The octal number (651.124)8 is equivalent to
a) (1A9.260)16
b) (1B0.160)16
c) (1A8.023)16
d) (1B0.289)16
Answer
Answer: a [Reason:] (651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010 0000)2
= (1A9.260)16
3. The decimal equivalent of (LM17) is given by
a) 491
b) 499
c) 497
d) 498
Answer
Answer: a [Reason:] (LM17) = 7 * 50 + 3 * 51 + M * 52 + L * 53
= 1 * 50 + 3 * 51 + 4 * 52 + 3 * 53 (L=3, M=4)
= 491.00
4. Convert hexadecimal to binary: (1E2H) = ?
a) 480
b) 483
c) 482
d) 484
Answer
Answer: c [Reason:] (1E2)16 = 1 * 162 + E * 161+ 2 * 160 = 256 + 224 + 2 = 482
5. (170)10 is equivalent to
a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
Answer
Answer: c [Reason:] Division Remainder
16) 170.00 ~~~~~~~~~ —
16) 10.00 ~~~~~~~~~ 10 = A
16) 00.00 ~~~~~~~~~ 10 = A
Hence, (170)10 = (AA)16
6. Convert in to decimal: (214)8 = ?
a) (140)10
b) (141)10
c) (142)10
d) (130)10
Answer
Answer: a [Reason:] (214)8 = 2 * 82 + 1 * 81 + 4 * 80
= 128.0 + 8.0 + 4 = (140)10
7. Convert (0.345)10 in to an octal number.
a) (0.1605)8
b) (0.2605)8
c) (0.1945)8
d) (0.2404)8
Answer
Answer: b [Reason:] 0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.2605)8
8. Convert from binary to decimal: (01011.1011)2 = ?
a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
Answer
Answer: a [Reason:] (01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10
9. Octal to binary conversion: (24)8 = ?
a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
Answer
Answer: c [Reason:] (24)8 = (010100)2
10. Convert binary to octal: (110110001010)2 = ?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
Answer
Answer: b [Reason:] (110110001010)2 = (6612)8
Set 4
1. How many outputs are present in a BCD decoder?
a) 4
b) 5
c) 15
d) 10
Answer
Answer: d [Reason:] A BCD to Decimal decoder has 10 number of outputs because the decimal digit’s range is from 0 to 9.
2. Which digital system translates coded characters into a more useful form?
a) Encoder
b) Display
c) Counter
d) Decoder
Answer
Answer: d [Reason:] Decoder converts the coded characters into our required data form.
3. What control signals may be necessary to operate a 1-line-to-16 line decoder?
a) Flasher circuit control signal
b) A LOW on all gate enable inputs
c) Input from a hexadecimal counter
d) A HIGH on all gate enable circuits
Answer
Answer: b [Reason:] A LOW on all gate enable inputs is necessary to operate a 1-line-to-16 line decoder because it is in inverted form always.
4. How many inputs are required for a 1-of-10 BCD decoder?
a) 4
b) 8
c) 10
d) 2
Answer
Answer: a [Reason:] ‘a’ is correct because 1-of-10 stands for BCD to decimal decoder.
5. A BCD decoder will have how many rows in its truth table?
a) 3
b) 9
c) 8
d) 10
Answer
Answer: a [Reason:] Because of it’s input ranges from 0 to 9.
6. How many possible outputs would a decoder have with a 6-bit binary input?
a) 32
b) 64
c) 128
d) 16
Answer
Answer: c [Reason:] The possible outputs would be: 2^6=64.
7. One way to convert BCD to binary using the hardware approach is:
a) By using MSI IC circuits
b) By using a keyboard encoder
c) By using an ALU
d) By using UART
Answer
Answer: a [Reason:] One way to convert BCD to binary using the hardware approach is MSI (medium scale integration) IC circuits.
8. How many inputs are required for a 1-of-16 decoder?
a) 2
b) 16
c) 8
d) 4
Answer
Answer: d [Reason:] ‘d’ is correct because 1-of-10 stands for BCD to decimal decoder.
9. A truth table with output columns numbered 0–15 may be for which type of decoder IC?
a) Hexadecimal 1-of-16
b) Dual octal outputs
c) Binary-to-hexadecimal
d) Hexadecimal-to-binary
Answer
Answer: a [Reason:] A truth table with output columns numbered 0–15 may be for Hexadecimal 1-of-16. Because, hexadecimal occupies less space in a system.
10. How can the active condition (HIGH or LOW) or the decoder output be determined from the logic symbol?
a) A bubble indicates active-HIGH
b) A bubble indicates active-LOW
c) A square indicates active-HIGH
d) A square indicates active-LOW
Answer
Answer: b [Reason:] A bubble indicates active-LOW in a decoder always.
Set 5
1. The basic building blocks of the arithmetic unit in a digital computers are
a) Subtractors
b) Adders
c) Multiplexer
d) None of the Mentioned
Answer
Answer: b [Reason:] The basic building blocks of the arithmetic unit in a digital computers are adders. Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade. By controlling the data inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
2. A digital system consists of _____ types of circuits.
a) 2
b) 3
c) 4
d) 5
Answer
Answer: a [Reason:] A digital system consists of two types of circuits and these are combinational and sequential logic circuit.
3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) None of the Mentioned
Answer
Answer: c [Reason:] In a combinational circuit, the output at any time depends only on the input values at that time.
4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
b) Intermediate values
c) Present input values
d) None of the Mentioned
Answer
Answer: c [Reason:] In a sequential circuit, the output at any time depends on the present input values as well as past output values.
5. Procedure for the design of combinational circuits are:
A. From the word description of the problem, identify the inputs and outputs and draw a block diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) None of the Mentioned
Answer
Answer: c [Reason:] The given arrangement in option c is the right sequence for the designing of the combinational circuits.
6. All logic operations can be obtained by means of
a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) AND, OR and NOT operations
Answer
Answer: d [Reason:] Since, the logic gates AND, OR and NOT are called as universal logic gates. It means that any operations can be obtained by implementation of these gates.
7. The design of an ALU is based on
a) Sequential logic
b) Combinational logic
c) Multiplexing
d) None of the Mentioned
Answer
Answer: b [Reason:] The design of an ALU is based on combinational logic. Because the unit has a regular pattern, it can be broken into identical stages connected in cascade through carries.
8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____ result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
Answer
Answer: d [Reason:] If the two numbers are unsigned, the bit conditions of interest are the output carry and a possible zero result.
9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) None of the Mentioned
Answer
Answer: c [Reason:] If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign of the result, a zero indication and an overflow condition.
10. The flag bits in an ALU is defined as
a) The total number of registers
b) The status bit conditions
c) The total number of control lines
d) All of the Mentioned
Answer
Answer: b [Reason:] In an ALU, status bit conditions are sometimes called condition code bits or flag bits.