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Multiple choice question for engineering

Set 1

1. The full form of ECL is
a) Emitter-collector logic
b) Emitter-complementary logic
c) Emitter-coupled logic
d) None of the Mentioned

View Answer

Answer: c [Reason:] The full form of ECL is emitter-coupled logic.

2. Which logic is the fastest of all the logic families?
a) TTL
b) ECL
c) HTL
d) DTL

View Answer

Answer: b [Reason:] ECL is the fastest of all the logic families because of the emitters of many transistors are coupled together which results the highest transmission rate.

3. The full form of CML is
a) Complementary mode logic
b) Current mode logic
c) Collector mode logic
d) None of the Mentioned

View Answer

Answer: c [Reason:] The full form of CML is Current Mode Logic.

4. Sometimes ECL can also be named as
a) EEL
b) CEL
c) CML
d) CCL

View Answer

Answer: c [Reason:] ECL can also be named as CML.

5. In an ECL the output is taken from
a) Emitter
b) Base
c) Collector
d) None of the Mentioned

View Answer

Answer: c [Reason:] Though, the emitters of the ECL are coupled together. So, the output will be taken from collector.

6. The ECL behaves as
a) NOT gate
b) NOR gate
c) NAND gate
d) AND gate

View Answer

Answer: b [Reason:] The ECL behaves as NOR gate because if any of the input voltages go high as compared to reference voltage, the output is low and vice versa for low input.

7. In ECL the fanout capability is
a) High
b) Low
c) Zero
d) Sometimes high and sometimes low

View Answer

Answer: a [Reason:] If the input impedance is high and the output resistance is low; as a result, the transistors change states quickly, gate delays are low, and the fanout capability is high.

8. ECL’s major disadvantage is that
a) It requires more power
b) It’s fanout capability is high
c) It creates more noise
d) None of the Mentioned

View Answer

Answer: a [Reason:] ECL’s major disadvantage is that each gate continuously draws current, which means it requires (and dissipates) significantly more power than those of other logic families.

9. The full form of SCFL is
a) Source-collector logic
b) Source-coupled logic
c) Source-complementary logic
d) None of the Mentioned

View Answer

Answer: b [Reason:] The full form of SCFL is source-coupled logic.

10. The equivalent of emitter-coupled logic made out of FETs is called
a) CML
b) SCFL
c) FECL
d) EFCL

View Answer

Answer: b [Reason:] The equivalent of emitter-coupled logic made out of FETs is called Source-coupled logic(SCFL).

11. ECL was invented in _______ by __________
a) 1956, Baker clamp
b) 1976, James R. Biard
c) 1956, Hannon S. Yourke
d) 1976, Yourke

View Answer

Answer: c [Reason:] ECL was invented in August 1956 at IBM by Hannon S Yourke.

12. At the time of invention, an ECL was called as
a) Source-coupled logic
b) Current Mode Logic
c) Current-steering logic
d) Emitter-coupled logic

View Answer

Answer: c [Reason:] At the time of invention, an ECL was called as current-steering logic.

13. The ECL circuits usually operates with
a) Negative voltage
b) Positive voltage
c) Grounded voltage
d) None of the Mentioned

View Answer

Answer: a [Reason:] The ECL circuits usually operate with negative power supplies (positive end of the supply is connected to ground), in comparison to other logic families in which negative end of the supply is grounded. It is done mainly to minimize the influence of the power supply variations on the logic levels as ECL is more sensitive to noise on the VCC and relatively immune to noise on VEE.

14. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of
a) ECL
b) VECL
c) PECL
d) LECL

View Answer

Answer: c [Reason:] Low voltage positive emitter coupled logic (LVPECL) is a power optimized version of PECL using a +3.3 V instead of 5 V supply.

Set 2

1. How many inputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 10
d) 16

View Answer

Answer: c [Reason:] Decimal-to-bcd converter decimal values are inputs which range from 0-9. So, total ten inputs a decimal-to-BCD encoder has.

2. How many outputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 12
d) 16

View Answer

Answer: a [Reason:] BCD means it should be of 4 bits. So, It has 4 outputs.

3. How is an encoder different from a decoder?
a) The output of an encoder is a binary code for 1-of-N input
b) The output of a decoder is a binary code for 1-of-N input
c) The output of an encoder is a binary code for N-of-1 output
d) The output of an decoder is a binary code for N-of-1 output

View Answer

Answer: a [Reason:] An encoder different from a decoder because of the output of an encoder is a binary code for 1-of-N input.

4. If we record any music in any recorder, such types of process is called
a) Multiplexing
b) Encoding
c) Decoding
d) None of the Mentioned

View Answer

Answer: b [Reason:] If we record any music in any recorder, it means that we are giving data to a recorder. So, such process is called encoding.

5. Can an encoder be a transducer?
a) Yes
b) No
c) May or may not be
d) None of the Mentioned

View Answer

Answer: a [Reason:] Of course, a transducer is a device which has the capability to emit data as well as to accept.

6. How many OR gates are required for a Decimal-to-bcd encoder?
a) 2
b) 10
c) 3
d) 4

View Answer

Answer: d [Reason:] This is clear from the diagram that it requires 4 OR gates: digital-circuits-questions-answers-encoders-q6.

7. How many OR gates are required for a octal-to-binary encoder?
a) 3
b) 2
c) 8
d) 10

View Answer

Answer: a [Reason:] There are 3 OR gates are required causing it has 3 outputs.

8. For 8-bit input encoder how many combinations are possible?
a) 8
b) 2^8
c) 4
d) 2^4

View Answer

Answer: b [Reason:] There are 2^8 combinations are possible for a 8-bit input encoder but out of which only 8 are used using 3 output lines. It is a disadvantage of encoder.

9. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using additional input known as
a) Enable
b) Disable
c) Strobe
d) None of the Mentioned

View Answer

Answer: a [Reason:] Such problems are resolved by using enable input, which behaves as active if it gets 0 as input.

10. Can an encoder be called as multiplexer?
a) No
b) Yes
c) Sometimes
d) Never

View Answer

Answer: b [Reason:] A multiplexer or MUX is a combination circuit that contains more than one input line, one output line and more than one selection line. Whereas, an encoder is also considered a type of multiplexer but without a single output line.

11. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
b) The lower value
c) Neither of the inputs
d) Both of the inputs

View Answer

Answer: a [Reason:] If two inputs are active on a priority encoder, the input of higher value will be coded in the output.

Set 3

1. The inverter can be produced with how many NAND gates?
a) 2
b) 1
c) 3
d) 4

View Answer

Answer: b [Reason:] The inverter can be produced with the help of single NAND gate, because we can combine both the inputs of the NAND gate together and make it single. It works as an inverter.

2. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output’s relation with the inputs?
a) The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s between the pulses
b) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s between the pulses
c) The exclusive-OR output is a 15 s pulse followed by a 40 s pulse
d) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse

View Answer

Answer: d [Reason:] When both the input pulses are high or low X-OR output is low. But when one of the input is high and another is low or vice-versa, output is high. In this problem for the first 20uS one input is high and another is low. So, obviously output is a high. for next 15uS both the input is high so output is low and for remaining 40uS(75-20-15) first input is still high and second one is low so output is high.

3. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
a) 2
b) 3
c) 4
d) 5

View Answer

Answer: a [Reason:] Since, in the given expression two inputs are complemented. So, we require two NOT gate at the input.

4. The carry look ahead adder is based on the principle of looking at the lower order bits of ________ and ________ if a high order carry is generated.
a) Addend, minuend
b) Minuend, subtrahend
c) Addend, minuend
d) Augend, addend

View Answer

Answer: d [Reason:] The carry look ahead adder is based on the principle of looking at the lower order bits of the augend and addend if a high order carry is generated.

5. What are carry generate combinations?
a) If all the input are same then a carry is generated
b) If all of the output are independent of the inputs
c) If all of the input are dependent on the output
d) None of the Mentioned

View Answer

Answer: b [Reason:] If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of input) and if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input). Such situation is known as carry generate combinations.

6. In serial addition, the addition is carried out
a) 3 bit per second
b) Byte by byte
c) Bit by bit
d) None of the Mentioned

View Answer

Answer: c [Reason:] In serial addition, the addition is carried out bit by bit.

7. How many shift registers are used in a 4 bit serial adder?
a) 4
b) 3
c) 2
d) 5

View Answer

Answer: c [Reason:] There are two shift registers are used in a 4-bit serial adder, which is used to store the numbers to be added serially.

8. A D flip-flop is used in a 4-bit serial adder, why?
a) It is used to invert the input of the full adder
b) It is used to store the output of the full adder
c) It is used to store the carry output of the full adder
d) None of the Mentioned

View Answer

Answer: c [Reason:] The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder so that it can be added to the next significant position of the numbers in the registers.

9. What is ripple carry adder?
a) The carry output of the lower order stage is connected to the carry input of the next higher order stage
b) The carry input of the lower order stage is connected to the carry output of the next higher order stage
c) The carry output of the higher order stage is connected to the carry input of the next lower order stage
d) None of the Mentioned

View Answer

Answer: a [Reason:] When the carry output of the lower order stage is connected to the carry input of the next higher order stage, such types of connection is called ripple carry adder in a 4-bit binary parallel adder.

10. If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be:
a) 0
b) 1
c) Not possible
d) None of the Mentioned

View Answer

Answer: b [Reason:] If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow output will be 1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till the next step (i.e 0 – 1 – 1 = 0, borrow = 1).

Set 4

1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling

View Answer

Answer: d [Reason:] Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.

2. One example of the use of an S-R flip-flop is as:
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator

View Answer

Answer: c [Reason:] The SR flip-flop is very effective in removing the effects of switch bounce.

3. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c [Reason:] The SR flip-flop actually has three inputs, Set, Reset and its current state.

4. When both inputs of a J-K flip-flop cycle, the output will
a) Be invalid
b) Change
c) Not change
d) Toggle

View Answer

Answer: c [Reason:] After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete).

5. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH

View Answer

Answer: a [Reason:] In D flip flop, when the clock is high then the out depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero.

6. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates

View Answer

Answer: c [Reason:] The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates.

7. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops

View Answer

Answer: b [Reason:] In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits.

8. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops

View Answer

Answer: a [Reason:] Combinational circuits are often faster than sequential circuits. Since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence.

9. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5

View Answer

Answer: a [Reason:] There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked.

10. The sequential circuit is also called
a) Flip-flop
b) Latch
c) Strobe
d) None of the Mentioned

View Answer

Answer: b [Reason:] The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.

11. The basic latch consist of
a) Two inverters
b) Two comparators
c) Two amplifiers
d) None of the Mentioned

View Answer

Answer: a [Reason:] The basic latch consist of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.

12. If Q = 0, the output is said to be
a) Set
b) Reset
c) Previous state
d) Current state

View Answer

Answer: a [Reason:] If Q = 0, the output is said to be set and reset for Q’ = 1.

13. The output of latches will remain in set/reset untill
a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) None of the Mentioned

View Answer

Answer: a [Reason:] The output of latches will remain in set/reset untill the trigger pulse is given to change the state.

14. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) None of the Mentioned

View Answer

Answer: a [Reason:] Trigger pulse is defined as a pulse that starts a cycle of operation.

15. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Both a & b

View Answer

Answer: c [Reason:] The cross-coupled connections from the output of one gate to the input of other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits.

Set 5

1. In parts of the processor, adders are used to calculate
a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned

View Answer

Answer: d [Reason:] In parts of the processor, adders are used to calculate addresses, table indices, increment and decrement operators, and similar operations.

2. Total number of inputs in a half adder is
a) 2
b) 3
c) 4
d) 1

View Answer

Answer: a [Reason:] Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs and carry is connected with the input of EXOR gates.

3. In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction

View Answer

Answer: b [Reason:] In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example carry is obtained after 1st addition (i.e. 1 + 1 = 1 0).

4. If A and B are the inputs of a half adder, the sum is given by
a) A AND B
b) A OR B
c) A XOR B
d) A EXOR B

View Answer

Answer: c [Reason:] If A and B are the inputs of a half adder, the sum is given by A XOR B.

5. If A and B are the inputs of a half adder, the carry is given by
a) A AND B
b) A OR B
c) A XOR B
d) A EXOR B

View Answer

Answer: a [Reason:] If A and B are the inputs of a half adder, the carry is given by: A(AND)B.

6. Half-adders have a major limitation in that they cannot
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) None of the Mentioned

View Answer

Answer: c [Reason:] Half-adders have a major limitation in that they cannot accept a carry bit from a previous stage, meaning that they cannot be chained together to add multi-bit numbers. However, the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being high.

7. The difference between half adder and full adder is
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned

View Answer

Answer: c [Reason:] Half adder has two inputs while full adder has three outputs; this is the difference between them.

8. If A, B and C are the inputs of a full adder then the sum is given by
a) A AND B AND C
b) A OR B AND C
c) A OR B OR C
d) A XOR B XOR C

View Answer

Answer: c [Reason:] If A, B and C are the inputs of a full adder then the sum is given by A OR B OR C.

9. If A, B and C are the inputs of a full adder then the carry is given by
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C

View Answer

Answer: a [Reason:] If A, B and C are the inputs of a full adder then the carry is given by A AND B OR (A OR B) AND C.

10. How many AND, OR and EXOR gates are required for the configuration of full adder
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1

View Answer

Answer: b [Reason:] There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder.