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# Multiple choice question for engineering

## Set 1

1. In digital logic, a counter is a device which
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) None of the Mentioned

Answer: b [Reason:] In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.

2. A counter circuit is usually constructed of
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) None of the Mentioned

Answer: c [Reason:] A counter circuit is usually constructed of a number of flip-flops connected in cascade.

3. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n-1
c) 0 to 2n+1
d) 0 to 2n+1/2

Answer: c [Reason:] The maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops is 0 to 2n+1.

4. How many types of counter are?
a) 2
b) 3
c) 4
d) 5

Answer: b [Reason:] Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode & (iii)modulus counter.

5. A decimal counter has ______ states.
a) 5
b) 10
c) 15
d) 20

Answer: b [Reason:] Decimal counter is also known as 10 stage counter. So, it has 10 states.

6. Ripple counters are also called
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters

Answer: b [Reason:] Ripple counters are also called asynchronous counter.

7. Synchronous counter is a type of
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters

Answer: c [Reason:] Medium Scale Integrated (MSI) is an operation in which the clock pulse is supplied to all the flip-flops simultaneously.

8. Three decade counter would have
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters

Answer: b [Reason:] Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD counters.

9. BCD counter is also known as
a) Parallel counter
c) Synchronous counter
d) VLSI counter

Answer: b [Reason:] BCD counter is also known as decade counter because both have the same number of stages.

10. The parallel outputs of a counter circuit represent the
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count

Answer: d [Reason:] The parallel outputs of a counter circuit represent the clock count.

## Set 2

1. In D flip-flop, D stands for
a) Distant
b) Delay
c) Desired
d) None of the Mentioned

Answer: b [Reason:] In D flip-flop, D stands for delay.

2. The D flip-flop has _______ input.
a) 1
b) 2
c) 3
d) 4

Answer: a [Reason:] The D flip-flop has one input.

3. The D flip-flop has ______ output/outputs.
a) 2
b) 3
c) 4
d) None of the Mentioned

Answer: a [Reason:] The D flip-flop has two outputs.

4. A D flip-flop can be constructed from an ______ flip-flop.
a) S-R
b) J-K
c) T
d) None of the Mentioned

Answer: a [Reason:] A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.

5. In D flip-flop, if clock input is LOW, the D input
a) Goes high
b) Has no effect
c) Goes low
d) None of the Mentioned

Answer: a [Reason:] In D flip-flop, if clock input is LOW, the D input has no effect, since the set and reset inputs of the NAND flip-flop are kept HIGH.

6. In D flip-flop, if clock input is HIGH & D=1, then output is
a) 0
b) 1
c) Forbidden
d) Toggle

Answer: a [Reason:] If clock input is HIGH & D=1, then output is 0. It can be observed from this diagram: Insert pics of D flip-flop.

7. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input

Answer: a [Reason:] By the truth table of D flip flop, we can observe that Q always depends on D. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q. Insert truth table of D flip-flop.

8. Which of the following is correct for a gated D flip-flop?
a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH

Answer: d [Reason:] If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop.

9. With regard to a D latch, ________
a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN’s input state

Answer: c [Reason:] Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input.

10. Which of the following is correct for a D latch?
a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled

Answer: b [Reason:] If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop.

11. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock

Answer: b [Reason:] The main phenomenon of D flip-flop is that the o/p will follow the i/p when enable pin is HIGH.

12. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1

Answer: d [Reason:] PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.

13. A positive edge-triggered D flip-flop will store a 1 when ________
a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH

Answer: b [Reason:] A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions from LOW to HIGH.

14. Why do the D flip-flops receives its designation or nomenclature as ‘Data Flip-flops’?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop
d) All of the Mentioned

Answer: c [Reason:] Due to its capability to transfer the data into flip-flop.

15. The characteristic equation of D-flip-flop implies that
a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state

Answer: d [Reason:] The characteristic equation of D flip-flop is given by: Q(n+1) = D; which indicates that the next state is independent of present state.

## Set 3

1. The word demultiplex means
a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor

Answer: d [Reason:] The word demultiplex means “one into many” and distributor. It is clear from the diagram:

2. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) None of the Mentioned

Answer: a [Reason:] For one input, the demultiplexer gives several outputs. That is why, it is called a data distributor.

3. Most demultiplexers facilitate which type of conversion?
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity

Answer: b [Reason:] Demultiplexer converts single input into multiple outputs.

4. In 1-to-4 demultiplexer, how many select lines are required?
a) 2
b) 3
c) 4
d) 5

Answer: a [Reason:] The formula for total no. of outputs is given by: 2^n, where n is the no. of select lines.

5. In a multiplexer the output depends on its
a) Data inputs
b) Select inputs
c) Select outputs
d) None of the Mentioned

Answer: b [Reason:] As the select input changes, the output of the multiplexer varies according to that input.

6. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be
a) Y0
b) Y1
c) Y2
d) Y3

Answer: b [Reason:] It can be calculated from the figure shown below: Here, the output Y1 = (C1)’C0X.

7. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be
a) Y0
b) Y1
c) Y2
d) Y3

Answer: d [Reason:] The output y3 = C1.C0.X.

8. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5

Answer: b [Reason:] The formula for total no. of outputs is given by: 2^n, where n is the no. of select lines. In this case n = 3.

9. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 4
d) 5

Answer: c [Reason:] The number of AND gates required will be equal to the number of outputs in a demultiplexer.

10. The output Q4 of this 1-to-8 demultiplexer is

a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) None of the Mentioned

Answer: c [Reason:] The output Y4 = Q2.(Q1)’.(Q0)’.I.

11. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138

Answer: a [Reason:] IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is inverted input.

## Set 4

1. Which of the following logic families has the highest maximum clock frequency?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS

Answer: b [Reason:] AS-TTL (Advanced Schottky) has maximum clock frequency of 105 MHz. S-TTL (Schottky High Speed TTL) has 100 MHz. Found nothing as HS-TTL. There are H and S separate TTL. HCMOS has 50 MHz clock frequency.

2. Why is the fan-out of CMOS gates frequency dependent?
a) Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate
b) When the frequency reaches the critical value the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal and this defines the upper operating frequency
c) The higher number of gates attached to the output the more frequently they will have to be serviced thus reducing the frequency at which each will be serviced with an input signal
d) The input gates of the FETs are predominantly capacitive and as the signal frequency increases the capacitive loading also increases thereby limiting the number of loads that may be attached to the output of the driving gate

Answer: d [Reason:] Actually power dissipation in CMOS circuits depends on clock frequency. As the frequency increases Pd also increases so fan-out depends on frequency.

3. Logic circuits that are designated as buffers, drivers or buffers/drivers are designed to have:
a) A greater current/voltage capability than an ordinary logic circuit
b) Greater input current/voltage capability than an ordinary logic circuit
c) A smaller output current/voltage capability than an ordinary logic
d) Greater the input and output current/voltage capability than an ordinary logic circuit

Answer: a [Reason:] Logic circuits that are designated as buffers, drivers or buffer/drivers are designed to have a greater current/voltage capability than an ordinary logic circuit.

4. Which of the following will not normally be found on a data sheet?
a) Minimum HIGH level output voltage
b) Maximum LOW level output voltage
c) Minimum LOW level output voltage
d) Maximum HIGH level input current

Answer: c [Reason:] Minimum LOW level output voltage will not normally be found on a data sheet.

5. Which of the following logic families has the shortest propagation delay?
a) S-TTL
b) AS-TTL
c) HS-TTL
d) HCMOS

Answer: b [Reason:] AS-TTL (Advanced Schottky) has maximum clock frequency that is 105 MHz. So, the propagation delay will be given by 1/105 sec which is the lowest one.

6. What is the static charge that can be stored by your body as you walk across a carpet?
a) 300 volts
b) 3000 volts
c) 30000 volts
d) Over 30000 volts

Answer: d [Reason:] When a person walks across a carpeted or tile floor electric charge builds up in the body due to the friction between shoes and floor material. If the friction static is greater the voltage potential develop in the body will be greater. You start act as a capacitor. This is called Electrostatic discharge. The potential static charge that can develop from walking on tile floors is greater than 15000 volts while carpeted floors can generate in excess of 30000 volts.

7. What must be done to interface TTL to CMOS?
a) A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the TTL
b) As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of the TTL is limited to five CMOS gates)
c) A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates
d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node

Answer: d [Reason:] To interface TTL to CMOS a pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node.

8. What causes low-power Schottky TTL to use less power than the 74XX series TTL?
a) The Schottky-clamped transistor
b) A larger value resistor
c) Using NAND gates
d) None of the Mentioned

Answer: b [Reason:] A larger value resistor causes low power low-power Schottky TTL to use less power than the 74XX series TTL.

9. What are the major differences between the 5400 and 7400 series of ICs?
a) The 5400 series are military grade and require tighter supply voltages and temperatures
b) The 5400 series are military grade and allow for a wider range of supply voltages and temperatures
c) The 7400 series are an improvement over the original 5400s
d) The 7400 series was originally developed by Texas Instruments and the 5400 series was brought out by National Semiconductors after TI’s patents expired as a second supply source

Answer: b [Reason:] The 5400 series are military grade and allow for a wider range of supply voltages and temperatures, these are the major differences between the 5400 and 7400 series of ICs.

10. Which of the following statements apply to CMOS devices?
a) The devices should not be inserted into circuits with the power on
b) All tools, test equipment and metal workbenches should be tied to earth ground
c) The devices should be stored and shipped in antistatic tubes or conductive foam
d) All of the Mentioned

Answer: d [Reason:] Both 5400 and 7400 IC’s were developed by TEXAS instruments only. The difference between the 5400 and the 7400 series is that the 5400 series devices operate over the military temperature range of -55°C to 125°C and the less expensive 7400 series devices need only operate over the commercial temperature range of 0°C to 70°C. In short, 5400 ICs are of military grade and 7400 ICs are of commercial grade.

## Set 5

1. Diode–transistor logic (DTL) is the direct ancestor of
a) Register-transistor logic
b) Transistor–transistor logic
c) High threshold logic
d) None of the Mentioned

Answer: b [Reason:] Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic.

2. In DTL logic gating function is performed by
a) Diode
b) Transistor
c) Register
d) Capacitor

Answer: a [Reason:] The logic gating function is performed by a diode network in DTL.

3. In DTL amplifying function is performed by
a) Diode
b) Transistor
c) Register
d) Capacitor

Answer: b [Reason:] The amplifying function is performed by a transistor in DTL.

4. How many stages a DTL consist of?
a) 2
b) 3
c) 4
d) 5

Answer: b [Reason:] The DTL circuit shown in the picture consists of three stages: an input diode logic stage, an intermediate level shifting stage and an output common-emitter amplifier stage.

5. The full form of CTDL is
a) Complemented transistor diode logic
b) Complemented transistor direct logic
c) Complementary transistor diode logic
d) None of the Mentioned

Answer: a [Reason:] The full form of CTDL is Complemented transistor diode logic.

6. The DTL propagation delay is relatively
a) Large
b) Small
c) Moderate
d) Negligible

Answer: a [Reason:] When the transistor goes into saturation from all inputs being high charge is stored in the base region. When it comes out of saturation (one input goes low) this charge has to be removed and will dominate the propagation time which results as a large propagation delay.

7. The way to speed up DTL is to add a across intermediate resister
a) Small “speed-up” capacitor
b) Large “speed-up” capacitor
c) Small “speed-up” transistor
d) Large ” speed-up” transistor

Answer: a [Reason:] One way to speed up DTL is to add a small “speed-up” capacitor across intermediate resister. The capacitor helps to turn off the transistor by removing the stored base charge; the capacitor also helps to turn on the transistor by increasing the initial base drive.

8. The process to avoid saturating the switching transistor is performed by
a) Baker clamp
b) James R. Biard
c) Chris Brown
d) None of the Mentioned

Answer: a [Reason:] Another way to speed up DTL other than adding a small “speed-up” capacitor across intermediate resister is to avoid saturating the switching transistor which can be done with a Baker clamp. The name Baker clamp is given at the name of Richard H. Baker, who described it in his 1956 technical report “Maximum Efficiency Switching Circuits”.

9. A major advantage of DTL over the earlier resistor–transistor logic is the
a) Increased fan out
b) Increased fan in
c) Decreased fan out
d) Decreased fan in

Answer: b [Reason:] A major advantage over the earlier resistor–transistor logic is the increased fan in.

10. To increase fan-out of the gate in DTL
a) An additional capacitor may be used
b) An additional resister may be used
c) An additional transistor and diode may be used
d) None of the Mentioned