Multiple choice question for engineering
Set 1
1. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?
a) a
b) b
c) c
d) d
Answer
Answer: d [Reason:] Here, the diagram of option d contains the OR gate followed by the AND gates, so it is in SOP form.
2. Which of the following logic expressions represents the logic diagram shown?
a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
Answer
Answer: d [Reason:] 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
3. The device shown here is most likely a ________
a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
Answer
Answer: d [Reason:] The given diagram is demultiplexer, because it takes single input & gives many outputs.
4. What type of logic circuit is represented by the figure shown below?
a) XOR
b) XNOR
c) AND
d) XAND
Answer
Answer: b [Reason:] After solving the circuit we get (AB)’+AB as output, which is XNOR operation.
5. For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct?
a) d
b) a
c) c
d) b
Answer
Answer: a [Reason:] When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
0 0 1
0 1 0
1 0 0
1 1 1.
6. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
Answer
Answer: b [Reason:] For decoding any number output must be high for that code and this is possible in D option only.
7. What is the indication of a short to ground in the output of a driving gate?
a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
Answer
Answer: b [Reason:] Short to ground in the output of a driving gate indicates of a signal loss to all load gates.
8. For the device shown here, assume the D input is LOW, both S inputs are LOW and the input is LOW. What is the status of the Y’ outputs?
a) All are HIGH
b) All are LOW
c) All but are LOW
d) All but are HIGH
Answer
Answer: d [Reason:] In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0.
9. The carry propagation can be expressed as ________
a) Cp = AB
b) Cp = A + B
c) Cp = A XOR B
d) Cp = A + B’
Answer
Answer: b [Reason:] This happens in parallel adders (where we try to add numbers in parallel via more than one adders). A carry propagation occurs when carry from one adder needs to be forwarded to other adder and that second adder is holding the computation (addition) because carry from first adder has not come yet. So, there is a slight delay for second adder and this is known as carry propagation.
10. 3 bits full adder contains
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Answer
Answer: d [Reason:] Three bits full adder requires 2^3 = 8 combinational circuits.
Set 2
1. Compatibility refers to
a) The output of a circuit should match with the input of another circuit
b) The output of a circuit should match with the input of the same circuit
c) The input of a circuit should match with the output of another circuit
d) None of the Mentioned
Answer
Answer: a [Reason:] The output(s) of a circuit or a system should match the input(s) of another circuit or system that has different electrical characteristics. This is referred to as compatibility.
2. The method of connecting a driving device to a loading device is known as
a) Compatibility
b) Interface
c) Sourcing
d) Sinking
Answer
Answer: b [Reason:] The method of connecting a driving device to a loading device is known as interface.
3. The first CML logic was introduced by General Electric in
a) 1960
b) 1981
c) 1961
d) 1990
Answer
Answer: c [Reason:] The first CML logic was introduced by General Electric in 1961.
4. Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they
a) Produces too much noise
b) Consume too much power
c) Have high fan-in
d) Have high fan-out
Answer
Answer: b [Reason:] Commercial ECL families are not nearly as popular as TTL and CMOS mainly because they consume too much power.
5. The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from
a) Fan-in
b) Fan-out
c) Saturation
d) Cut-off
Answer
Answer: c [Reason:] The key to propagation delay in bipolar logic family is to prevent the transistors in a gate from saturation.
6. Schottky families prevent the saturating using
a) Transistors
b) Schottky transistors
c) Diodes
d) Schottky diodes
Answer
Answer: d [Reason:] Schottky families prevent the saturating using Schottky diodes across the base-collector junctions of transistors.
7. The basic idea of basic CML circuit came from an
a) Inverter
b) Buffer
c) Transistor
d) Both inverter and buffer
Answer
Answer: d [Reason:] Since, this circuit has both inverting and non-inverting output. So, It behaves like an inverter/buffer.
8. The full form of MECL is
a) Mono emitter coupled logic
b) Motorola emitter coupled logic
c) Motorola emitter capacitor logic
d) Both mono emitter and motorola coupled logic
Answer
Answer: b [Reason:] The full form of MECL is Motorola emitter coupled logic.
9. Motorola has offered MECL circuits in ______ logic families.
a) 3
b) 4
c) 5
d) 6
Answer
Answer: c [Reason:] Motorola has offered MECL circuits in five logic families: MECL I, MECL II, MECL III, MECL 10000 (MECL 10K) and MECL 10H000 (MECL 10KH).
10. The latest entrant to the ECL family is
a) ECL 10K
b) ECL 100K
c) ECL 1000K
d) ECL 10000K
Answer
Answer: b [Reason:] The latest entrant to the ECL family is ECL 100K, having 6-digit part numbers. This family offers functions, in general, different from those offered by 10K series. This family operates with a reduced power supply voltage -4.5 V, has shorter propagation delay of 0.75 ns, and transition time of 0.7 ns. However, the power consumption per gate is about 40 mW.
11. All input of NOR as low produces result as
a) Low
b) Mid
c) High
d) None of the Mentioned
Answer
Answer: c [Reason:] According to the properties of NOR gate, if all the input of NOR as low produces result as high.
12. In RTL NOR gate, the output is at logic 1 only when all the inputs are at
a) logic 0
b) logic 1
c) +10v
d) None of the Mentioned
Answer
Answer: a [Reason:] RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only when all the inputs are at logic 0.
Set 3
1. Controlled inverter is also known as
a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) None of the Mentioned
Answer
Answer: c [Reason:] Controlled inverter is also known as controlled buffer and NOT gate as well.
2. Why XOR gate is called an inverter?
a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) None of the Mentioned
Answer
Answer: c [Reason:] The XOR (Exclusive Or) gate has a true output when the two inputs are different. When one input is true, the output is the inversion of the other. When one input is false, the output is the non-inversion of the other.
3. Controlled buffers can be useful
a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
d) All of the Mentioned
Answer
Answer: a [Reason:] Controlled buffers can be useful when you have a wire (often called a bus) whose value should match the output of one of several components. By placing a controlled buffer between each component output and the bus, you can control whether that component’s output is fed onto the bus or not.
4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
Answer
Answer: a [Reason:] EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs HIGH or both inputs are LOW.
5. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
Answer
Answer: d [Reason:] Documentation is a set of documents provided on paper, or online, or on digital or analog media, such as audio tape or CDs. So, for the implementation of micro function good documentation is necessary.
6. What is the major difference between half-adders and full-adders?
a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
Answer
Answer: c [Reason:] Half adders have only two inputs A and B. When we add two 4 bit binary number like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is 1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second bits addition of the number. So, half adders are useless. But in full adders, one more carry input is present, so that, if carry of one stage is present, it can be added with the next stage as it is done in normal addition. So, therefore, full adders have a carry input capability.
7. The binary subtraction of 0 – 0 = ?
a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
Answer
Answer: a [Reason:] The binary subtraction of 0 – 0 = 0.
8. How many basic binary subtraction operations are possible?
a) 1
b) 4
c) 3
d) 2
Answer
Answer: b [Reason:] There are 4 binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
9. When performing subtraction by addition in the 2’s-complement system:
a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
Answer
Answer: c [Reason:] When performing subtraction by addition in the 2’s-complement system, the minuend is left in its original form and the subtrahend is changed to its 2’s-complement.
10. What are the two types of basic adder circuits?
a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
Answer
Answer: b [Reason:] There are two types of adder circuits: half-adder and full-adder.
11. Which of the following is correct for full adders?
a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
Answer
Answer: d [Reason:] By using maximum of two half adders we can make a full adder.
12. The selector inputs to an arithmetic/logic unit (ALU) determine the:
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
Answer
Answer: b [Reason:] An ALU performs basic arithmetic and logic operations. Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are comparisons of values such as NOT, AND and OR.
Set 4
1. What is the difference between a 7490 and a 7493?
a) 7490 is a MOD-10, 7493 is a MOD-16
b) 7490 is a MOD-16, 7493 is a MOD-10
c) 7490 is a MOD-12, 7493 is a MOD-16
d) 7490 is a MOD-10, 7493 is a MOD-12
Answer
Answer: a [Reason:] the difference between a 7490 and a 7493 is that 7490 is a MOD-10, 7493 is a MOD-16 counter.
2. How many different states does a 2-bit asynchronous counter have?
a) 1
b) 4
c) 2
d) 8
Answer
Answer: b [Reason:] 2^2 = 4.
3. A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________
a) 10 kHz
b) 20 kHz
c) 30 kHz
d) 60 kHz
Answer
Answer: c [Reason:] Cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. So, 5*8*10=400. Applied clock frequency = 12 MHz; hence, the lowest output frequency possible is 12MHz/400=30 kHz.
4. Which one is a 4-bit binary ripple counter?
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
Answer
Answer: b [Reason:] IC 7493 is a 4-bit binary ripple counter.
5. IC 7493 consist of
a) 4 S-R flip-flop
b) 4 J-K flip-flop
c) 4 master-slave flip-flop
d) 4 D flip-flop
Answer
Answer: c [Reason:] IC 7493 consist of 4 master-slave flip-flop.
6. A reset input is used in IC 7493, why?
a) For increment of bit by 1
b) For decrement of bit by 1
c) For reset the counter
d) None of the Mentioned
Answer
Answer: c [Reason:] The reset inputs are used to reset the counter to 0000.
7. In a 4-bit binary ripple counter, four master-slave flip-flops are internally connected to provide a ________ bit counter.
a) Divide-by-2 & divide-by-6
b) Divide-by-6 & divide-by-8
c) Divide-by-2 & divide-by-8
d) Divide-by-4 & divide-by-8
Answer
Answer: c [Reason:] In a 4-bit binary ripple counter, four master-slave flip-flops are internally connected to provide a Divide-by-2 & divide-by-8 bit counter.
8. Which of the following is decade counter?
a) IC 7493
b) IC 7490
c) IC 7491
d) IC 7492
Answer
Answer: b [Reason:] IC 7490 is called as decade counter or MOD-10.
9. In a 4-bit decade counter, four master-slave flip-flops are internally connected to provide a ________ bit counter.
a) Divide-by-2 & divide-by-6
b) Divide-by-6 & divide-by-8
c) Divide-by-2 & divide-by-5
d) Divide-by-4 & divide-by-8
Answer
Answer: c [Reason:] In a decade counter, four master-slave flip-flops are internally connected to provide a Divide-by-2 & divide-by-5 bit counter.
10. Reset inputs are used in IC 7490, why?
a) For increment of bit by 1
b) For decrement of bit by 1
c) For reset the counter
d) None of the Mentioned
Answer
Answer: c [Reason:] The reset inputs are used to reset the counter to 0000.
11. The set inputs are used in a decade counter, why?
a) To set the counter to 0011
b) To set the counter to 1000
c) To set the counter to 1001
d) To set the counter to 0001
Answer
Answer: c [Reason:] The set inputs are used in a decade counter to set set the counter to 1001.
12. List which pins need to be connected together on a 7493 to make a MOD-12 counter.
a) 12 to 1, 11 to 3, 9 to 2
b) 12 to 1, 11 to 3, 12 to 2
c) 12 to 1, 11 to 3, 8 to 2
d) 12 to 1, 11 to 3, 1 to 2
Answer
Answer: c [Reason:] It is clear from the diagram shown below: 12 & 1 are clear pins, 11 & 3 are clock pins, 8 & 2 are input for 7493 FF.
13. Ripple counter IC has
a) 10 pins
b) 11 pins
c) 12 pins
d) 14 pins
Answer
Answer: d [Reason:] Ripple counter IC has 14 pins.
14. Integrated-circuit counter chips are used in numerous applications including:
a) Timing operations, counting operations, sequencing, and frequency multiplication
b) Timing operations, counting operations, sequencing, and frequency division
c) Timing operations, decoding operations, sequencing, and frequency multiplication
d) Data generation, counting operations, sequencing, and frequency multiplication
Answer
Answer: b [Reason:] There is no integrated Circuits employed for frequency multiplication. In the options a, c, d we have given frequency multiplication. So, they are not the correct answers.
15. What is the difference between a 7490 and a 7492?
a) 7490 is a MOD-12, 7492 is a MOD-10
b) 7490 is a MOD-12, 7492 is a MOD-16
c) 7490 is a MOD-16, 7492 is a MOD-10
d) 7490 is a MOD-10, 7492 is a MOD-12
Answer
Answer: d [Reason:] From the properties of both ICs, we have 7490 is a MOD-10, 7492 is a MOD-12.
Set 5
1. A ripple counter’s speed is limited by the propagation delay of:
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer
Answer: a [Reason:] A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account.
2. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Answer
Answer: d [Reason:] Each bit = 12ns. 5 bits = 12ns * 5 = 60ns.
3. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
Answer
Answer: d [Reason:] The given counter is ripple(asynchronous), so only it would take 4 * 15 = 60ns.
4. A ripple counter’s speed is limited by the propagation delay of:
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer
Answer: a [Reason:] A ripple counter’s speed is limited by the propagation delay of each flip-flop.
5. What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
Answer
Answer: d [Reason:] Maximum propagation delay is the longest delay between an input changing value and the output changing value. Hence, 22 * 4 = 88.
6. The main drawback of a ripple counter is that
a) It has a cumulative settling time
b) It has a distributive settling time
c) It has a productive settling time
d) None of the Mentioned
Answer
Answer: a [Reason:] The main drawback of a ripple counter is that it has a cumulative settling time (i.e. another bit is transmitted just after one consequently).
7. A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec, the maximum clock frequency that can be used is equal to
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
Answer
Answer: c [Reason:] Propagation Delay for one FF is 50ns. For 4 FF = 50 x 4 = 200ns. Clock frequency = 1/200ns = 5 MHz.
8. As the number of flip flops are increased, the total propagation delay of
a) Ripple counter increases but that of synchronous counter remains the same
b) Both ripple and synchronous counters increase
c) Both ripple and synchronous counters remain the same
d) Ripple counter remains the same but that of synchronous counter increases
Answer
Answer: a [Reason:] In ripple counter the clock pulses are applied to one flip- flop only. Hence, as the number of flip-flops increases the delay increases. In synchronous counter, clock pulses to all flip-flops are applied simultaneously.
9. A reliable method for eliminating decoder spikes is the technique called ________
a) Strobing
b) Feeding
c) Wagging
d) Waving
Answer
Answer: a [Reason:] A reliable method for eliminating decoder spikes is the technique called strobing.
10. A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because
a) It is a random event
b) It occurs less frequently than the normal decoded output
c) It is very fast
d) All of the Mentioned
Answer
Answer: d [Reason:] A glitch that appears on the decoded output of a ripple counter is often difficult to see on an oscilloscope because it is a random event and very fast and it occurs less frequently than the normal decoded output.
11. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”. The third and fourth stages will
a) Continue to count with correct outputs
b) Continue to count but have incorrect outputs
c) Stop counting
d) Turn into molten silicon
Answer
Answer: c [Reason:] Because next flip-flop’s input depends on the output of the previous flip-flop.