# Multiple choice question for engineering

## Set 1

1. Controlled inverter is also known as

a) Controlled buffer

b) NOT gate

c) Both controlled buffer and NOT gate

d) None of the Mentioned

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2. Why XOR gate is called an inverter?

a) Because of the same input

b) Because of the same output

c) It behaves like a NOT gate

d) None of the Mentioned

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3. Controlled buffers can be useful

a) To control the circuit’s output into the bus

b) In comparison of component’s output with its input

c) In increasing the output from its low input

d) All of the Mentioned

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4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is

a) Ex-NOR gate

b) OR gate

c) Ex-OR gate

d) NAND gate

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5. What is the first thing you will need if you are going to use a macro-function?

a) A complicated design project

b) An experienced design engineer

c) Good documentation

d) Experience in HDL

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6. What is the major difference between half-adders and full-adders?

a) Full-adders are made up of two half-adders

b) Full adders can handle double-digit numbers

c) Full adders have a carry input capability

d) Half adders can handle only single-digit numbers

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7. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0

b) Difference = 1, borrow = 0

c) Difference = 1, borrow = 1

d) Difference = 0, borrow = 1

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8. How many basic binary subtraction operations are possible?

a) 1

b) 4

c) 3

d) 2

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9. When performing subtraction by addition in the 2’s-complement system:

a) The minuend and the subtrahend are both changed to the 2’s-complement

b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form

c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement

d) The minuend and subtrahend are both left in their original form

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10. What are the two types of basic adder circuits?

a) Sum and carry

b) Half-adder and full-adder

c) Asynchronous and synchronous

d) One and two’s-complement

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11. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers

b) Full adders are used to make half adders

c) Full adders are limited to two inputs since there are only two binary digits

d) In a parallel full adder, the first stage may be a half adder

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12. The selector inputs to an arithmetic/logic unit (ALU) determine the:

a) Selection of the IC

b) Arithmetic or logic function

c) Data word selection

d) Clock frequency to be used

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## Set 2

1. The addition of binary numbers:

11011011010 + 010100101 = ?

a) 0111001000

b) 1100110110

c) 11101111111

d) 10011010011

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2. Perform binary addition: 101101 + 011011 = ?

a) 011010

b) 1010100

c) 101110

d) 1001000

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2. Perform binary subtraction: 101111 – 010101 = ?

a) 100100

b) 010101

c) 011010

d) 011001

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3. The result obtained after (100101 – 011110) is

a) 000111

b) 111000

c) 010101

d) 101010

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4. Multiply the binary number: 01001 × 01011 = ?

a) 001100011

b) 110011100

c) 010100110

d) 101010111

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5. 100101 × 0110 = ?

a) 1011001111

b) 0100110011

c) 101111110

d) 0110100101

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6. On multiplication of (10.10) and (01.01), we get

a) 101.0010

b) 0010.101

c) 011.0010

d) 110.0011

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7. Divide the binary numbers: 111101 ÷ 1001 and find the remainder

a) 0010

b) 1010

c) 1100

d) 0011

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9. Divide: 011010000 ÷ 0101 = ?

a) 10001

b) 10100

c) 11001

d) 01000

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10. Subtract: 101101 – 001011 = ?

a) 100010

b) 010110

c) 110101

d) 101100

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## Set 3

1. How many natural states will there be in a 4-bit ripple counter?

a) 4

b) 8

c) 16

d) 32

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^{4}= 16 states.

2. A ripple counter’s speed is limited by the propagation delay of:

a) Each flip-flop

b) All flip-flops and gates

c) The flip-flops only with gates

d) Only circuit gates

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3. One of the major drawbacks to the use of asynchronous counters is that:

a) Low-frequency applications are limited because of internal propagation delays

b) High-frequency applications are limited because of internal propagation delays

c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications

d) Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications

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4. Internal propagation delay of asynchronous counter is removed by

a) Ripple counter

b) Ring counter

c) Modulus counter

d) Synchronous counter

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5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?

a) The output increases by 1

b) The output decreases by 1

c) The output word increases by 2

d) The output word decreases by 2

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6. How many flip-flops are required to construct a decade counter?

a) 4

b) 8

c) 5

d) 10

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^{4}=16and2

^{3}=8, therefore, 4 flip flops needed.

7. The terminal count of a typical modulus-10 binary counter is

a) 0000

b) 1010

c) 1001

d) 1111

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8. How many different states does a 3-bit asynchronous counter have?

a) 2

b) 4

c) 8

d) 16

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^{3}=8, so 8 states a 3-bit asynchronous counter have.

9. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is

a) 12 ms

b) 24 ns

c) 48 ns

d) 60 ns

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10. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?

a) 1

b) 2

c) 8

d) 15

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^{4}– 1 = 15. So, total transitional states are 15.

11. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of

a) 15 ns

b) 30 ns

c) 45 ns

d) 60 ns

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12. Three cascaded decade counters will divide the input frequency by

a) 10

b) 20

c) 100

d) 1000

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13. A ripple counter’s speed is limited by the propagation delay of:

a) Each flip-flop

b) All flip-flops and gates

c) The flip-flops only with gates

d) Only circuit gates

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14. A 4-bit counter has a maximum modulus of

a) 3

b) 6

c) 8

d) 16

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^{4}= 16.

15. A principle regarding most display decoders is that when the correct input is present, the related output will switch

a) HIGH

b) To high impedance

c) To an open

d) LOW

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## Set 4

1. Which of the following statements are true?

a) Asynchronous events does not occur at the same time

b) Asynchronous events are controlled by a clock

c) Synchronous events does not need a clock to control them

d) Only asynchronous events need a control clock

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2. A down counter using n-flip-flops count

a) Downward from a maximum count

b) Upward from a minimum count

c) Downward from a minimum to maximum count

d) None of the Mentioned

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3. UP Counter is

a) It counts in upward manner

b) It count in down ward manner

c) It counts in both the direction

d) None of the mentioned

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4. DOWN counter is

a) It counts in upward manner

b) It count in downward manner

c) It counts in both the direction

d) None of the mentioned

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5. How many different states does a 3-bit asynchronous down counter have?

a) 2

b) 4

c) 6

d) 8

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6. In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop goes from HIGH to LOW.

a) MSB flip-flop

b) LSB flip-flop

c) Master slave flip-flop

d) None of the Mentioned

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7. In a 3-bit asynchronous down counter, the initial content is

a) 000

b) 111

c) 010

d) 101

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8. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes

a) 000

b) 111

c) 101

d) 010

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9. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes

a) 000

b) 111

c) 101

d) 010

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10. The hexadecimal equivalent of 15,536 is ________

a) 3CB0

b) 3C66

c) 63C0

d) 6300

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11. In order to check the CLR function of a counter

a) Apply the active level to the CLR input and check all of the Q outputs to see if they are all in their reset state

b) Ground the CLR input and check to be sure that all of the Q outputs are LOW

c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH

d) Connect the CLR to its correct active level while clocking the counter; check to make sure that all of the Q outputs are toggling

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## Set 5

1. The decimal number system represent the decimal number in the form of

a) Hexadecimal

b) Binary coded

c) Octal

d) Decimal

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2. 2^9 input circuit will have total of

a) 32 entries

b) 128 entries

c) 256 entries

d) 512 entries

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3. BCD adder can be constructed with 3 IC packages each of

a) 2 bits

b) 3 bits

c) 4 bits

d) 5 bits

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4. The output sum of two decimal digits can be represented in

a) Gray Code

b) Excess-3

c) BCD

d) Hexadecimal

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5. The addition of two decimal digits in BCD can be done through

a) BCD adder

b) Full adder

c) Ripple carry adder

d) Carry look ahead

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6. 3 bits full adder contains

a) 3 combinational inputs

b) 4 combinational inputs

c) 6 combinational inputs

d) 8 combinational inputs

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7. The simplified expression of full adder carry is

a) c = xy+xz+yz

b) c = xy+xz

c) c = xy+yz

d) c = x+y+z

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8. Complement of F’ gives back

a) F’

b) F

c) FF

d) undefined variable

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9. Decimal digit in BCD can be represented by

a) 1 input line

b) 2 input lines

c) 3 input lines

d) 4 input lines

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10. The number of logic gates and the way of their interconnections can be classified as

a) Logical network

b) System network

c) Circuit network

d) Gate network