Multiple choice question for engineering
Set 1
1. Which is a top-down method of analyzing risks?
a) FTA
b) FMEA
c) Hazards
d) Damages
Answer
Answer: a [Reason:] The FTA is Fault tree analysis which is a top-down method of analyzing risks. It starts with a damage and comes up with the reasons for the damage. The analysis is done graphically by using gates.
2. What is FTA?
a) free tree analysis
b) fault tree analysis
c) fault top analysis
d) free top analysis
Answer
Answer: b [Reason:] The FTA is also known as the Fault tree analysis which is a top-down method of analyzing risks. The analysis starts with a damage and comes up with the reasons for the damage. The analysis can be checked graphically by using gates.
3. Which gate is used in the geometrical representation, if a single event causes hazards?
a) AND
b) NOT
c) NAND
d) OR
Answer
Answer: d [Reason:] The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous. Similarly, AND gates are used in the graphical representation, if several events cause hazards.
4. Which analysis uses the graphical representation of hazards?
a) Power model
b) FTA
c) FMEA
d) First power model
Answer
Answer: b [Reason:] The FTA is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous.
5. Which gate is used in the graphical representation, if several events cause hazard?
a) OR
b) NOT
c) AND
d) NAND
Answer
Answer: c [Reason:] The fault tree analysis is done graphically by using gates. The main gates used are AND gates and OR gates. The AND gates are used in the graphical representation, if several events cause hazards.
6. What is FMEA?
a) fast mode and effect analysis
b) front mode and effect analysis
c) false mode and effect analysis
d) failure mode and effect analysis
Answer
Answer: d [Reason:] The FMEA is the failure mode and the effect analysis, in which the analysis starts at the components and tries to estimate their reliability.
7. Which of the following can compute the exact number of clock cycles required to run an application?
a) layout model
b) coarse-grained model
c) fine-grained model
d) register-transaction model
Answer
Answer: c [Reason:] The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.
8. Which model is capable of reflecting the bidirectional transfer of information?
a) switch-level model
b) gate level
c) layout model
d) circuit-level model
Answer
Answer: a [Reason:] The switch model can be used in the simulation of the transistors since the transistor is the very basic component in a switch. It is capable of reflecting bidirectional transferring of the information.
Set 2
1. Which of the following is a set of specially selected input patterns?
a) test pattern
b) debugger pattern
c) bit pattern
d) byte pattern
Answer
Answer: a [Reason:] While testing any devices or embedded systems, we apply some selected inputs which is known as the test pattern and observe the output. This output is compared with the expected output. The test patterns are normally applied to the already manufactured systems.
2. Which is applied to a manufactured system?
a) bit pattern
b) parity pattern
c) test pattern
d) byte pattern
Answer
Answer: c [Reason:] For testing any devices or embedded systems, we use some sort of selected inputs which is known as the test pattern and observe the output and is compared with the expected output. This test patterns are normally applied to the manufactured systems.
3. Which of the following is based on fault models?
a) alpha-numeric pattern
b) test pattern
c) bit pattern
d) parity pattern
Answer
Answer: b [Reason:] The test pattern generation is normally based on the fault models and this model is also known as the stuck-at model. The test pattern is based on certain assumption, that is why it is called as the stuck-at model.
4. Which is also called stuck-at model?
a) byte pattern
b) parity pattern
c) bit pattern
d) test pattern
Answer
Answer: d [Reason:] The test pattern generation is basically based on the fault models and this type of model is also known as the stuck-at model. These test patterns are based on certain assumption, hence it is known as the stuck-at model.
5. How is the quality of the test pattern evaluated?
a) fault coverage
b) test pattern
c) size of the test pattern
d) number of errors
Answer
Answer: a [Reason:] The quality of the test pattern can be evaluated on the basis of the fault coverage. It is the percentage of potential faults that can be found for a given test pattern set, that is fault coverage equals the number of detectable faults for a given test pattern set divided by the number of faults possible due to the fault model.
6. What is DfT?
a) discrete Fourier transform
b) discrete for transaction
c) design for testability
d) design Fourier transform
Answer
Answer: c [Reason:] The design of testability or DfT is the process of designing for the better testability.
7. Which of the following is also known as boundary scan?
a) test pattern
b) JTAG
c) FSM
d) CRC
Answer
Answer: b [Reason:] The JTAG is a technique for connecting scan chains of several chips and is also known as boundary scan.
8. What does BILBO stand for?
a) built-in logic block observer
b) bounded input bounded output
c) built-in loading block observer
d) built-in local block observer
Answer
Answer: a [Reason:] The BILBO or the built-in logic block observer is proposed as a circuit combining, test response compaction, test pattern generation, and serial input/output capabilities.
9. What is CRC?
a) code reducing check
b) counter reducing check
c) counting redundancy check
d) cyclic redundancy check
Answer
Answer: d [Reason:] The CRC or the cyclic redundancy check is the error detecting code which is commonly used in the storage device and the digital networks.
10. What is FSM?
a) Fourier state machine
b) finite state machine
c) fast state machine
d) free state machine
Answer
Answer: b [Reason:] The FSM is the finite state machine. It will be having a finite number of states and is used to design both the sequential logic circuit and the computer programs. It can be used for testing the scan design in the testing techniques.
11. Which of the following have flip-flops which are connected to form shift registers?
a) scan design
b) test pattern
c) bit pattern
d) CRC
Answer
Answer: a [Reason:] All the flip-flop storing states are connected to form a shift register in the scan design. It is a kind of test path.
Set 3
1. Which of the buffers has a single piece of linear contiguous memory?
a) circular buffer
b) linear buffer
c) directional buffer
d) double buffer
Answer
Answer: b [Reason:] The linear buffer is contiguous memory which is a single piece memory that is controlled by the pointers whose address increments linearly.
2. Which buffer will lose data when it is full?
a) linear buffer
b) circular buffer
c) directional buffer
d) double buffer
Answer
Answer: a [Reason:] The linear buffer has a single piece of contiguous memory which is controlled by the pointers whose address increments linearly and it will lose data when it is full and fail to provide data when it is empty.
3. Which of the following buffers loses the incoming data when it is full?
a) circular buffer
b) double buffer
c) linear buffer
d) directional buffer
Answer
Answer: c [Reason:] The linear buffer will lose the incoming data when full such that the data it contains become older, which is known as the overrun condition.
4. Which state of the linear buffer will provide old data, when it is empty?
a) overrun
b) critical timing
c) peak overshoot
d) underrun
Answer
Answer: d [Reason:] In the linear buffer, when it is empty it will provide the old data, usually the last entry so that the processor will continue to process the incorrect data potentially, and this condition is known as underrun.
5. Which state of the linear buffer loses its incoming data when full?
a) underrun
b) overrun
c) critical time
d) pointer
Answer
Answer: b [Reason:] In the overrun condition, the linear buffer will lose the incoming data when the buffer is filled and the data it contains become older.
6. Which technique can solve the errors in the linear buffer?
a) low water mark
b) high water mark
c) low and high water mark
d) pointer
Answer
Answer: c [Reason:] The errors in the linear buffering includes the loss of data especially during the regular sampling which can be avoided by the pointers that are checked against certain values and this result is used for fetching more data. These points are known as the low water mark and the high water mark.
7. Which of the following is similar to the high and low water marks at the coast?
a) minimum and maximum water level
b) low and high water mark
c) small and big water mark
d) medium and high water mark
Answer
Answer: b [Reason:] There are some errors in the linear buffering which includes the loss of data especially in the regular sampling. This can be avoided by the pointers that are checked against certain values and the result is used to fetch more data. These points are known as the low water mark and the high water mark. It is named so because it is similar to the high and low water marks seen at the coast which indicates the maximum and minimum levels that the tidal water will fall and rise.
8. Which of the following determines the number of entries in the buffer?
a) low water mark
b) high water mark
c) low and high water mark
d) small and big water mark
Answer
Answer: a [Reason:] The number of entries below the low water mark determines the number of entries the buffer has and the amount of time which is available to fill the buffer before empties and the condition is known as underrun.
9. Which of the following determines the number of empty entries?
a) low water tank
b) high water tank
c) small water tank
d) big water tank
Answer
Answer: b [Reason:] The high water tank measures the number of empty entries, that is the number of empty entries above the high water tank determines the length of time which is available to stop the filling of the buffer and it can prevent the data loss through overrunning.
10. In which case, the buffer is used by two software task?
a) single buffer
b) linear buffer
c) double buffer
d) directional buffer
Answer
Answer: a [Reason:] In the single buffer, the buffer is used by two software tasks to insert or extract information. The problem with this buffer is that the water level is above or below, and the free space that is used to fill the buffer does not lie in the correct location.
11. Which buffer is important for the signal data?
a) double buffer
b) single buffer
c) linear buffer
d) directional buffer
Answer
Answer: d [Reason:] The directional buffer is used for the signal data or for the data which is sampled periodically. The data must be kept in the same order in order to preserve it in a chronological order.
12. Which of the following uses two buffers?
a) linear buffer
b) single buffer
c) double buffer
d) directional buffer
Answer
Answer: c [Reason:] The double buffer uses buffers as its name suggest, one buffer is for filling and the other buffer is for extraction.
13. Which of the following uses a single low water tank and a next data pointer?
a) single buffer
b) double buffer
c) directional buffer
d) linear buffer
Answer
Answer: a [Reason:] The single buffer uses a single low water tank and a next data pointer. The next data pointer is used for accessing the next entry that should be extracted.
Set 4
1. Which of the following is standardised as IEEE 1364?
a) C
b) C++
c) FORTRAN
d) Verilog
Answer
Answer: d [Reason:] The Verilog is a hardware description language which was developed for modelling hardware and electronic devices. This was later standardised by IEEE standard 1364.
2. Who developed the Verilog?
a) Moorby
b) Thomas
c) Russell and Ritchie
d) Moorby and Thomson
Answer
Answer: d [Reason:] The Verilog is a hardware description language which was developed by Moorby and Thomson in 1991 and it was standardised as IEEE standard 1364. The Verilog is modelled for the electronics devices.
3. Which versions of the Verilog is known as System Verilog?
a) Verilog version 3.0
b) Verilog version 1.0
c) Verilog version 1.5
d) Verilog version 4.0
Answer
Answer: a [Reason:] The Verilog versions 3.0 and 3.1 is called as the System Verilog. These include several extensions to the Verilog version 2.0.
4. Which of the following is a Verilog version 1.0?
a) IEEE standard 1394-1995
b) IEEE standard 1364-1995
c) IEEE standard 1394-2001
d) IEEE standard 1364-2001
Answer
Answer: b [Reason:] The IEEE standard 1364-1995 is the first version of the Verilog and IEEE standard 1394-2001 is the Verilog version 2.0.
5. Which of the following provides multiple-valued logic with eight signal strength?
a) Verilog
b) VHDL
c) C
d) C++
Answer
Answer: a [Reason:] The Verilog supports the multiple-valued logic with eight different signal strength but Verilog is less flexible compared to the VHDL, that is, it allows the hardware entities to be instantiated in loops which help to build up a structural description.
6. Which of the following is a superset of Verilog?
a) Verilog
b) VHDL
c) System Verilog
d) System VHDL
Answer
Answer: c [Reason:] The System Verilog is a superset of the Verilog. But later on, System Verilog and Verilog has merged into a new IEEE standard 1800-2009.
7. Which hardware description language is more flexible?
a) VHDL
b) Verilog
c) C
d) C++
Answer
Answer: a [Reason:] The Verilog is less flexible compared to the VHDL, that is, it allows the hardware entities to be instantiated in loops which help to build up a structural description. But Verilog, on the other hand, focuses more on the built-in features.
8. Which of the following provide more features for transistor-level descriptions?
a) C++
b) C
c) VHDL
d) Verilog
Answer
Answer: d [Reason:] The Verilog offers more features than the VHDL but VHDL is more flexible compared to the Verilog. The Verilog can provide transistor-level descriptions but the VHDL cannot provide this description.
9. Which hardware description language is popular in the US?
a) System Verilog
b) System log
c) Verilog
d) VHDL
Answer
Answer: c [Reason:] Verilog and VHDL are almost similar in their characteristics and have a similar number of users. The VHDL is more popular in Europe whereas Verilog is more popular in the US.
10. Which hardware description language is more popular in Europe?
a) VHDL
b) System log
c) Verilog
d) C
Answer
Answer: a [Reason:] The Verilog and VHDL are hardware description language and these are similar in their characteristics and have similar number of users. The VHDL is more popular in Europe. The Verilog is more popular in the US.
Set 5
1. Which of the following language can describe the hardware?
a) C
b) C++
c) JAVA
d) VHDL
Answer
Answer: d [Reason:] The VHDL is the hardware description language which describes the hardware whereas the C, C++ and JAVA are software languages.
2. What do VHDL stand for?
a) Verilog hardware description language
b) VHSIC hardware description language
c) very hardware description language
d) VMEbus description language
Answer
Answer: b [Reason:] VHDL is the VHSIC(very high speed integrated circuit) hardware description language which was developed by three companies, IBM, Intermetrics and Texas Instruments and the first version of the VHDL is established in the year 1984 and later on the VHDL is standardised by the IEEE.
3. What do VHSIC stand for?
a) very high speed integrated chip
b) very high sensor integrated chip
c) Verilog system integrated chip
d) Verilog speed integrated chip
Answer
Answer: a [Reason:] The VHSIC stands for very high speed integrated chip and VHDL was designed in the context of the VHSIC, developed by the department of defence in the US.
4. Each unit to be modelled in a VHDL design is known as
a) behavioural model
b) design architecture
c) design entity
d) structural model
Answer
Answer: c [Reason:] Each unit to be modelled in a VHDL design is known as the design entity or the VHDL entity. There are two types of ingredients are used. These are the entity declaration and the architecture declaration.
5. Which of the following are capable of displaying output signal waveforms resulting from stimuli applied to the inputs?
a) VHDL simulator
b) VHDL emulator
c) VHDL debugger
d) VHDL locater
Answer
Answer: a [Reason:] The VHDL simulator is capable of displaying the output signal waveforms which results from the stimuli or trigger applied to the input.
6. Which of the following describes the connections between the entity port and the local component?
a) port map
b) one-to-one map
c) many-to-one map
d) one-to-many maps
Answer
Answer: a [Reason:] The port map describes the connection between the entity port and the local component. The component is declared by component declaration and the entity ports are mapped with the port mapping.
7. Who proposed the CSA theory?
a) Russell
b) Jacome
c) Hayes
d) Ritchie
Answer
Answer: c [Reason:] The CSA theory is proposed by Hayes and this theory is based on the systematic way of building up value sets.
8. Which of the following is a systematic way of building up value sets?
a) CSA theory
b) Bayes theorem
c) Russell’s power mode;
d) first power model
Answer
Answer: a [Reason:] The CSA theory is proposed by Hayes. The theory is based on the systematic way of building up value sets, that is the electronics design system uses a variety of value sets, like 2, 3 etc. The goal of developing discrete value sets is to avoid the problems of solving network equations.
9. Which of the following is an abstraction of the signal impedance?
a) level
b) strength
c) size
d) nature
Answer
Answer: b [Reason:] The systems contain electrical signals of different strengths and it needs to compute the strength and the logic level resulting from a connection of two or more sources of electrical signals. The strength is the abstraction of the signal impedance.
10. Which of the following is an abstraction of the signal voltage?
a) level
b) strength
c) nature
d) size
Answer
Answer: a [Reason:] Most of the systems contain electrical signals of different strengths and levels. The level of the signal is the abstraction of the signal voltage and the strength is the abstraction of the signal impedance.